MPC8540 datasheet(259/1302 Pages) FREESCALE

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Registers for Branch Operations

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-9

6.4

Registers for Branch Operations

This section describes registers that support Book E branch and CR operations.

6.4.1

Condition Register (CR)

Table 6-3. XER Field Description

Bits

Name

Description

Summary overflow. Set when an instruction (except mtspr) sets the overflow bit. Once set, SO

remains set until it is cleared by mtspr[XER] or mcrxr. SO is not altered by compare instructions or

by other instructions (except mtspr[XER] and mcrxr) that cannot overflow. Executing mtspr[XER],

supplying the values 0 for SO and 1 for OV, causes SO to be cleared and OV to be set.

Overflow. X-form add, subtract from, and negate instructions having OE = 1 set OV if the carry out of

bit 32 is not equal to the carry out of bit 33, and clear OV otherwise to indicate a signed overflow.

X-form multiply low word and divide word instructions having OE = 1 set OV if the result cannot be

represented in 32 bits (mullwo, divwo, and divwuo) and clear OV otherwise. OV is not altered by

compare instructions or by other instructions (except mtspr[XER] and mcrxr) that cannot overflow.

Carry. Add carrying, subtract from carrying, add extended, and subtract from extended instructions

set CA if there is a carry out of bit 32 and clear it otherwise. CA can be used to indicate unsigned

overflow for add and subtract operations that set CA. Shift right algebraic word instructions set CA if

any 1 bits are shifted out of a negative operand and clear CA otherwise. Compare instructions and

instructions that cannot carry (except Shift Right Algebraic Word, mtspr[XER], and mcrxr) do not

affect CA.

35–56

—

Reserved, should be cleared.

57–63

No. of

bytes

Supports emulation of load and store string instructions. Specifies the number of bytes to be

transferred by a load string indexed or store string indexed instruction.

35 36

39 40

43 44

47 48

51 52

55 56

59 60

Field

CR0

CR1

CR2

CR3

CR4

CR5

CR6

CR7

Reset

All zeros

R/W

Figure 6-3. Condition Register (CR)

Table 6-4. BI Operand Settings for CR Fields

CRn Bits CR Bits

Description

CR0[0]

00000 Negative (LT)—Set when the result is negative.

For SPE APU vector compare and vector test instructions:

Set if the high-order element of rA is equal to the high-order element of rB; cleared

otherwise.

CR0[1]

00001 Positive (GT)—Set when the result is positive (and not zero).

For SPE APU vector compare and vector test instructions:

Set if the low-order element of rA is equal to the low-order element of rB; cleared

otherwise.

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