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MPC8540 Datasheet(PDF) 254 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 254 Page - Freescale Semiconductor, Inc |
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254 / 1302 page  MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 6-4 Freescale Semiconductor Core Register Summary • Section 6.7, “Interrupt Registers” • Section 6.8, “Software-Use SPRs (SPRG0–SPRG7 and USPRG0),” describes Book E–defined SPRs defined for software use. • Section 6.9, “Branch Target Buffer (BTB) Registers,” describes e500-specific registers defined to support the e500 BTBs. • Section 6.10, “Hardware Implementation-Dependent Registers,” describes HID0 and HID1. • Section 6.11, “L1 Cache Configuration Registers” • Section 6.12, “MMU Registers” • Section 6.13, “Debug Registers” • Section 6.14, “Signal Processing and Embedded Floating-Point Status and Control Register (SPEFSCR)” The e500 core implements 64-bit GPRs, the upper 32 bits of which are used only with 64-bit load, store, and merge instructions. 6.2.1 Special-Purpose Registers (SPRs) Table 6-1 summarizes SPRs defined in Book E. The SPR numbers are used in the instruction mnemonics. Bit 5 in an SPR number indicates whether an SPR is accessible from user- or supervisor-level software. An mtspr or mfspr instruction that specifies an unsupported SPR number is considered an invalid instruction. Table 6-1. Book E Special-Purpose Registers (by SPR Abbreviation) SPR Abbreviatio n Name Defined SPR Number Access Superviso r Only Section/ Page Decimal Binary CSRR0 Critical save/restore register 0 58 00001 11010 Read/Write Yes 6.7.1.1/6-18 CSRR1 Critical save/restore register 1 59 00001 11011 Read/Write Yes 6.7.1.2/6-18 CTR Count register 9 00000 01001 Read/Write No 6.4.3/6-11 DAC1 Data address compare 1 316 01001 11100 Read/Write Yes 6.13.4/6-48 DAC2 Data address compare 2 317 01001 11101 DBCR0 Debug control register 0 308 01001 10100 Read/Write Yes 6.13.1/6-42 DBCR1 Debug control register 1 309 01001 10101 Read/Write Yes DBCR2 Debug control register 2 310 01001 10110 Read/Write Yes DBSR Debug status register 304 01001 10000 Read/Clear1 Yes 6.13.2/6-46 DEAR Data exception address register 61 00001 11101 Read/Write Yes 6.7.1.5/6-19 DEC Decrementer 22 00000 10110 Read/Write Yes 6.6.4/6-17 DECAR Decrementer auto-reload 54 00001 10110 Write-only ESR Exception syndrome register 62 00001 11110 Read/Write Yes 6.7.1.8/6-20 |
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