ISL78840ASxH, ISL78841ASxH, ISL78843ASxH, ISL78845ASxH, ISL738840ASEH, ISL738841ASEH, ISL738843ASEH, ISL738845ASEH

FN7952 Rev.4.00

Page 12 of 18

Feb 25, 2020

The COMP pin is clamped to the voltage on capacitor C1 plus a

base-emitter junction by transistor Q1. C1 is charged from VREF

through resistor R1 and the base current of Q1. At power-up C1 is

fully discharged, COMP is at ~0.7V, and the duty cycle is zero. As

C1 charges, the voltage on COMP increases and the duty cycle

increases in proportion to the voltage on C1. When COMP

reaches the steady state operating point, the control loop takes

over and soft-start is complete. C1 continues to charge up to

VREF and no longer affects COMP. During power-down, diode D1

quickly discharges C1 so that the soft-start circuit is properly

initialized prior to the next power-on sequence.

Gate Drive

The ISL7884xASxH and ISL73884xASEH devices are capable of

sourcing and sinking 1A peak current. To limit the peak current

through the IC, an optional external resistor may be placed

between the totem-pole output of the IC (OUT pin) and the gate of

the MOSFET. This small series resistor also damps any

oscillations caused by the resonant tank of the parasitic

inductances in the traces of the board and the FETs input

capacitance. TID environment of >50krads requires the use of a

bleeder resistor of 10k from the OUT pin to GND.

Slope Compensation

For applications where the maximum duty cycle is less than 50%,

slope compensation may be used to improve noise immunity,

particularly at lighter loads. The amount of slope compensation

required for noise immunity is determined empirically, but is

generally about 10% of the full scale current feedback signal. For

applications where the duty cycle is greater than 50%, slope

compensation is required to prevent instability.

Slope compensation may be accomplished by summing an

external ramp with the current feedback signal or by subtracting

the external ramp from the voltage feedback error signal. Adding

the external ramp to the current feedback signal is the more

popular method.

From the small signal current-mode model [1] it can be shown

that the naturally-sampled modulator gain, Fm, without slope

compensation is calculated in Equation 6:

where Sn is the slope of the sawtooth signal and tSW is the

duration of the half-cycle. When an external ramp is added, the

modulator gain becomes Equation 7:

where Se is slope of the external ramp and becomes Equation 8:

The criteria for determining the correct amount of external ramp

can be determined by appropriately setting the damping factor of

the double-pole located at the switching frequency. The

double-pole will be critically damped if the Q-factor is set to 1,

over-damped for Q < 1 and under-damped for Q > 1. An

under-damped condition may result in current loop instability.

where D is the percent of on-time during a switching cycle.

Setting Q = 1 and solving for Se yields Equation 10:

Because Sn and Se are the on-time slopes of the current ramp

and the external ramp, respectively, they can be multiplied by tON

to obtain the voltage change that occurs during tON.

where Vn is the change in the current feedback signal (I) during

the on-time and Ve is the voltage that must be added by the

external ramp.

For a flyback converter, Vn can be solved in terms of input

voltage, current transducer components and primary inductance,

yielding Equation 12:

where RCS is the current sense resistor, tSW is the switching

period, Lp is the primary inductance, VIN is the minimum input

voltage and D is the maximum duty cycle.

The current sense signal at the end of the ON time for CCM

operation is Equation 13:

where VCS is the voltage across the current sense resistor, Ls is

the secondary winding inductance and IO is the output current at

current limit. Equation 13 assumes the voltage drop across the

output rectifier is negligible.

Because the peak current limit threshold is 1.00V, the total

current feedback signal plus the external ramp voltage must sum

to this value when the output load is at the current limit threshold

as shown in Equation 14:

Substituting Equations 12 and 13 into Equation 14 and solving

for RCS yields Equation 15:

Fm

1

SntSW

------------------

=

(EQ. 6)

Fm

1

Sn Se

+

tsw

-----------------------------------

1

mcSntSW

--------------------------

==

(EQ. 7)

mc

1

Se

Sn

-------

+

=

(EQ. 8)

Q

1

 m

c 1D

–

 0.5

–



-------------------------------------------------

=

(EQ. 9)

Se

Sn

1



--- 0.5

+



 1

1D

–

------------- 1

–





=

(EQ. 10)

Ve

Vn

1



--- 0.5

+



 1

1D

–

------------- 1

–





=

(EQ. 11)

Ve

Dt



SW VIN RCS



Lp

-------------------------------------------------- 1



--- 0.5

+



 1

1D

–

------------- 1

–





=

V

(EQ. 12)

VCS

NS RCS



NP

------------------------ IO

1D

–

 V

O t



sw

2Ls

--------------------------------------------

+







=

V

(EQ. 13)

Ve VCS

+

1V

=

(EQ. 14)

RCS

1

DTsw VIN



Lp

---------------------------------

1



--- 0.5

+

1D

–

------------------ 1

–











Ns

Np

-------

IO

1D

–

 V

O tsw



2Ls

--------------------------------------------

+









+

-------------------------------------------------------------------------------------------------------------------------------------------------------

=

(EQ. 15)