SPEAR-07-NC03 datasheet(61/194 Pages) STMICROELECTRONICS

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SPEAR-07-NC03

6 Blocks description

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6.2.4.30 MMC Control Register

Mnemonic

: MMC_CTRL_REG

Address

: 0x3000_3500

Default value

: 0x0000_2F72

This register establishes the operating mode of the management counters.

MAX_FRM_SIZE

: These bits indicate the value of the Maximum Packet Size for the transmitted

frames to be counted as long frames.

RESET_ON_READ

: When set the counter will be reset to 0 after read.

CNTR_ROLL_OVER: When set, counters after reaching the maximum value start again from 0.

CNTR_RESET

: When set, all counters will be reset to 0.

6.2.4.31 MMC Interrupt High Register

Mnemonic

: MMC_INT_HI_REG

Address

: 0x3000_33504

Default value

: 0x0000_0000

Bit

Field name

Access

31 – 14

Reserved

13 – 03

MAX_FRM_SIZE

RESET_ON_READ

CNTR_ROLL_OVER

CNTR_RESET

Bit

Field name

Access

31 – 12

Reserved

TX_EXC_DEFER_FRMS

TX_CRS_ERROR_FRMS

TX_ABORTED_FRMS

TX_LATE_COL_FRMS

TX_DEFERRED_FRMS

TX_MUL_COL_FRMS

TX_SINGLE_COL_FRMS

TX_BAD_FRMS

TX_FIFO_UND_FRMS

TX_BROADCAST_FRMS

TX_MULTICAST_FRMS

TX_UNICAST_FRMS

SPEAR-07-NC03 Datasheet(PDF) 61 Page - STMicroelectronics

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