13

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A Product Line of

Diodes Incorporated

PI6CBE33085

www.diodes.com

June 2022

Diodes Incorporated

PI6CBE33085

Document Number DS43625 Rev 2-2

Symbol

Parameters

Condition

Min.

Typ.

Max.

Spec

Limit Units

tjPHPLL_

QPI_UPI

Integrated Phase Jitter PLL

Mode (RMS)(1,5)

QPI and UPI, 100M or 133.33MHz,

4.8Gbps, 6.4Gbps 12UI

—

0.16

—

0.5

ps

QPI and UPI, 100MHz, 8.0Gbps, 12UI

—

0.1

—

0.3

ps

QPI and UPI, 100MHz, <11.4Gbps,

12UI

—

0.08

—

0.2

ps

tjPH_QPI_

UPI

Fanout Buffer Mode

Additive Integrated Phase

Jitter (RMS)(1,5,10)

QPI and UPI, 100M or 133.33MHz,

4.8Gbps, 6.4Gbps 12UI

—

0.03

—

—

ps (p-p)

QPI and UPI, 100MHz, 8.0Gbps, 12UI

—

0.03

—

—

ps

QPI and UPI, 100MHz, <11.4Gbps,

12UI

—

0.02

—

—

ps

tjPH_IFUPI

PLL Mode IF-UPI phase

jitter

Low bandwidth

—

0.1

—

—

ps

High bandwidth

—

0.17

—

—

ps

Fanout Buffer Mode IF-

UPI phase jitter

—

0.06

—

—

ps

tjPH_

DB2000Q

Fanout Buffer Mode

DB2000Q phase jitter

—

28

—

—

fs

Note:

1. Guaranteed by design and characterization—not 100% tested in production.

2. Measured from differential waveform.

3. Slew rate is measured through the Vswing voltage range centered around differential 0V, within ±150mV window.

4. Slew rate matching is measured through ±75mV window centered around differential zero.

5. See http://www.pcisig.com for complete specs.

6. Sample size of at least 100k cycles. This can be extrapolated to 108ps pk-pk @ 1M cycles for a BER of 10-12.

7. Duty cycle distortion is the difference in duty cycle between the output and input clock when the device is operated in the PLL bypass mode.

8. The Min and Max values of each BW setting track each other, low BW max will never occur with high BW min.

9. Applies to all differential outputs.

10. For additive jitter RMS value is calculated by the following equation = SQRT [(total jitter)*2 - (input jitter)*2].

11. PCIe 5.0 v0.9 specification.

HCSL Output AC Characteristics (Jitter)