AP64100Q

Document number: DS43575 Rev. 1 - 2

11 of 26

www.diodes.com

July 2021

© Diodes Incorporated

AP64100Q

Application Information

1

Pulse Width Modulation (PWM) Operation

The AP64100Q device is an automotive-compliant, 3.8V-to-40V input, 1A output, EMI friendly, fully integrated synchronous buck converter. Refer

to the block diagram in Figure 3. The device employs fixed-frequency peak current mode control. The switching frequency is adjustable from

100kHz to 2.2MHz through either of two modes, resistor timing or external clock synchronization, to allow optimizing either power efficiency or

external component size. The internal

clock’s rising edge initiates turning on the integrated high-side power MOSFET, Q1, for each cycle. When

Q1 is on, the inductor current rises linearly and the device charges the output capacitor. The current across Q1 is sensed and converted to a

voltage with a ratio of RT via the CSA block. The CSA output is combined with an internal slope compensation, SE, resulting in VSUM. When VSUM

rises higher than the COMP node, the device turns off Q1 and turns on the low-side power MOSFET, Q2. The inductor current decreases when

Q2 is on. On the rising edge of next clock cycle, Q2 turns off and Q1 turns on. This sequence repeats every clock cycle.

The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load

current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the

increased load current. This feedback loop regulates the output voltage. The internal slope compensation circuitry prevents subharmonic

oscillation when the duty cycle is greater than 50% for peak current mode control.

The peak current mode control and built-in 2ms soft-start time simplify the AP64100Q footprint.

2

Pulse Frequency Modulation (PFM) Operation

In heavy load conditions, the AP64100Q operates in forced PWM mode. As the load current decreases, the internal COMP node voltage also

decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further.

The voltage at which COMP is clamped corresponds to the 400mA PFM peak inductor current limit. As the load current approaches zero, the

AP64100Q enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 60mA,

zero cross detection circuitry on the low-side power MOSFET, Q2, forces it off. The buck converter does not sink current from the output when the

output load is light and while the device is in PFM. Because the AP64100Q works in PFM during light load conditions, it can achieve power

efficiency of up to 88% at a 5mA load condition.

The quiescent current of the AP64100Q is 25

μA typical under a no-load, non-switching condition.

3

Enable

When disabled, the device shutdown supply

current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.18V,

rising), the AP64100Q enables all functions and the device initiates the soft-start phase. The EN pin is a high-voltage pin and can be directly

connected to VIN to automatically start up the device as VIN increases. An internal 1.5µA pull-up current source connected from the internal LDO-

regulated VCC to the EN pin guarantees that if EN is left floating, the device still automatically enables once the voltage reaches the EN logic high

threshold. The AP64100Q has a built-in 2ms soft-start time to prevent output voltage overshoot and inrush current. When the EN voltage falls

below its logic low threshold (typical 1.09V, falling), the internal SS voltage discharges to ground and device operation disables.

The EN pin can also be used to adjust the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details.

Alternatively, a small ceramic capacitor can be added from EN to GND. When EN is not driven externally, this capacitor increases the time needed

for the EN pin voltage to reach its logic high threshold, which delays the startup of the output voltage. This is useful when sequencing multiple

power rails to minimize input inrush current. When the EN pin voltage starts from 0V, the amount of capacitance for a given delay time is

approximated by:

������������[������������] ≈ ������. ������������ ∙ ������������[������������]

Eq. 1

Where:



Cd is the time delay capacitance in nF



td is the delay time in ms