AP64100Q

Document number: DS43575 Rev. 1 - 2

17 of 26

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July 2021

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AP64100Q

Application Information (continued)

16

External Loop Compensation Design

When the COMP pin is not connected to GND, the COMP pin is active for external loop compensation. The regulator uses a constant frequency,

peak current mode control architecture to achieve a fast loop response. The inductor is not considered as a state variable since its peak current is

constant. Thus, the system becomes a single-order system. For loop stabilization, it is simpler to design a Type II compensator for current mode

control than it is to design a Type III compensator for voltage mode control. Peak current mode control has an inherent input voltage feed-forward

function to achieve good line regulation. Figure 28 shows the small signal model of the synchronous buck regulator.

+

–

1:D

in

L

Rc

COUT

-Av(S)

He(S)

Ro

+

SE

Fm

RT

K(S)

L

comp

Tv(S)

in

o

Ti(S)

Figure 28. Small Signal Model of Buck Regulator

Where:



Tv(S) is the voltage loop



Ti(S) is the current loop



K(S) is the voltage sense gain



-Av(S) is the feedback compensation gain



He(S) is the current sampling function



Fm is the PWM comparator gain



Vin is the DC input voltage



D is the duty cycle



Rc is the ESR of the output capacitor, COUT



Ro is the output load resistance



v̂in is the AC small-signal input voltage



îin is the AC small-signal input current



d̂ is the modulation of the duty cycle



îL is the AC small signal of the inductor current



v̂o is the AC small signal of output voltage



v̂comp is the AC small signal voltage of the compensation network