AX88178

USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller

6.2.1

Detailed Register Description

6.2.1.1 Rx/Tx SRAM Read Register (02h, read only)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

AA [7:0]

Reserved

B [3:0]

0h

C [3:0]

DD [7:0] in Data stage

EE [7:0] in Data stage

FF [7:0] in Data stage

GG [7:0] in Data stage

HH [7:0] in Data stage

II [7:0] in Data stage

JJ [7:0] in Data stage

KK [7:0] in Data stage

{B [3:0], AA [7:0]}: The read address of RX or TX SRAM.

C [0]: RAM selection.

0: indicates to read from RX SRAM.

1: indicates to read from TX SRAM.

C [3:1]: Reserved.

{DD [7:0], EE [7:0], FF [7:0], GG [7:0], HH [7:0], II [7:0], JJ [7:0], KK [7:0]}: The 64-bits of data presented in Data

stage are the data to be written to RX or TX SRAM.

6.2.1.2 Rx/Tx SRAM Write Register (03h, write only)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

AA [7:0]

Reserved

B [3:0]

Reserved

C [3:0]

DD [7:0] in Data stage

EE [7:0] in Data stage

FF [7:0] in Data stage

GG [7:0] in Data stage

HH [7:0] in Data stage

II [7:0] in Data stage

JJ [7:0] in Data stage

KK [7:0] in Data stage

{B [3:0], AA [7:0]}: The write address of RX or TX SRAM.

C [0]: RAM selection.

0: indicates to write to RX SRAM.

1: indicates to write to TX SRAM.

C [3:1]: Reserved.

{DD [7:0], EE [7:0], FF [7:0], GG [7:0], HH [7:0], II [7:0], JJ [7:0], KK [7:0]}: The 64-bits of data presented in Data

stage are the data to be written to RX or TX SRAM.

6.2.1.3 Software Serial Management Control Register (06h, write only)

When software needs to access to Ethernet PHY’s internal registers, one has to first issue this command to request the

ownership of Serial Management Interface. The ownership status of the interface can be retrieved from Serial

Management Status Register.

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