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AX88178 Datasheet(PDF) 32 Page - ASIX Electronics Corporation |
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AX88178 Datasheet(HTML) 32 Page - ASIX Electronics Corporation |
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32 / 37 page ![]() AX88178 USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller Trclk Trch Trcl RX_CLK Trs Trh RXD [3:0] RX_DV, RX_ER Symbol Description Min Typ Max Units Trclk RX_CLK clock cycle time *1 - 40.0 - ns Trch RX_CLK clock high time *2 - 20.0 - ns Trcl RX_CLK clock low time *2 - 20.0 - ns Trs RXD [3:0], RX_DV, and RX_ER setup time 3.0 - - ns Trh RXD [3:0], RX_DV, and RX_ER hold time 0.5 - - ns *1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns. *2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns. 7.4.6 Station Management Timing MDC Tod Tclk Tch Tcl Th Ts MDIO (as output) MDIO (as input) Symbol Description Min Typ Max Units Tclk MDC clock cycle time - 666 - ns Tch MDC clock high time - 333 - ns Tcl MDC clock low time - 333 - ns Tod MDC clock falling edge to MDIO output delay 0 - 2 ns Ts MDIO data input setup time 10 - - ns Th MDIO data input hold time 0 - - ns ASIX ELECTRONICS CORPORATION 32 |
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