NXP Semiconductors

SE050

Plug & Trust Secure Element

SCL, SDA pads in open-drain mode.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

tRW

Reset pulse width (RST_N low)

without entering Power-down

mode

40

400

μs

tRDSLP

Reset pulse width (RST_N low)

to enter Power-down mode

500

μs

tWKP

Wake-up time from Power-

down mode

fCLKmin < fCLK < fCLKmax

-

8

10

μs

level triggered ext.int.

-

8

10

μs

tWKPIO

Pad LOW time for wake-up

from Power-down mode

edge triggered ext.int.

-

8

10

μs

tWKPRST RST_N LOW time for wake-up

from Power-down mode

40

-

μs

CPIN

Pin capacitances RST_N,

I2C_SDA, /I2C_SCL

Test frequency = 1 MHz; Tamb

= 25 °C

-

10.5

pF

Table 14. Electrical AC characteristics of I2C_SDA, I2C_SCL, and RST_N[1]; VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS =

0 V; Tamb = -40 °C to + 105 °C...continued

[1]

All appropriately marked values are typical values and only referenced for information. They are subject to change without notice.

[2]

tr is defined as rise time between 30 % and 70 % of the signal amplitude.

tf is defined as fall time between 70 % and 30 % of the signal amplitude.

[3]

Wakeup from power down: if clock stretching disabled and I2C_SCL=400 kHz; the wakeup time will not be sufficient under the rare condition where host

sends the first command during the time where SE is just entering power down; in this case the SE will send an R block to request retransmission from the

host

[4]

Wakeup from power down: if clock stretching disabled and I2C_SCL=1 MHz; the wakeup time will not be sufficient to receive the first host command; the

SE will send an R block to request retransmission from the host

[5]

Low glitches below 0.4 V on pin ENA and Vin, Vout, Vcc larger than 30 ns cause Power-On-Reset, respectively entering deep power-down mode.

aaa-037451

70 % level

Vhigh

tCLKW

CLK (et al)

Vlow

0.5 VDD

1/fCLK

tfCLK

tfRST

tfIO

trCLK

trRST

trIO

30 % level

1) During AC testing the inputs RST_N, I2C_SDA, I2C_SCL are driven at 0 V to +0.3 V for a LOW

input level and at VCC -0.3 V to VCC for a HIGH input level. Clock period and signal pulse (duty

cycle) timing is measured at 50 % of VCC.

2) tr is defined as rise time between 30 % and 70 % of the signal amplitude. tf is defined as fall

time between 70 % and 30 % of the signal amplitude.

Figure 10. External clock drive and AC test timing reference points of I2C_SDA, I2C_SCL,

and RST_N (see 1) and 2)) in open-drain mode

Conditions: VCC = 1.8 V ± 10 % or 3 V ± 10 % V; VSS = 0 V; Tamb = -40 °C to +105 °C, unless otherwise specified. Typical

values are only referenced for information. They are subject to change without notice.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

Input/Output: IO1/IO2

trIO

I/O Input rise time

Input/reception mode

[1]

[2]

1

μs

Table 15. Electrical AC characteristics of IO1, IO2, CLK and RST_N (ISO7816 interface)

SE050

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© 2022 NXP B.V. All rights reserved.

Product data sheet

Rev. 3.5 — 22 August 2022

504935

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