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SE050 Datasheet(PDF) 9 Page - NXP Semiconductors |
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SE050 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 32 page ![]() NXP Semiconductors SE050 Plug & Trust Secure Element aaa-037450 1 0 0 1 target address 0 0 0 R/W Figure 3. target address The I2C controller interface is supposed to be used with target devices that need to be securely written and read. This interface features a maximum SCL clock rate of 400 kHz. I2C controller can only be used when the I2C target interface is active. 4.1.1 Supported I2C frequencies The SE050 I2C target interface supports the I2C high-speed mode with a maximum SCL clock of up to 3.4 MHz when clock stretching is enabled. In case clock stretching is disabled the maximum supported SCL clock frequency is 1.0 MHz. This is the default setting for the SE050 new generation products, SE050E. In the following SE050 configurations, A,B,C,D,F, the Clock stretching is enabled by default. Clock stretching will occur for frequencies higher than 600 kHz. In case clock stretching is not supported by the I2C controller a dedicated configuration with disabled clock stretching has to be used to ensure the above mentioned maximum clock frequency. The SE050 I2C controller interface supports maximum 400 kHz SCL clock frequency. For more details on the features of each configuration, refer to [4]. 4.2 ISO7816 and ISO14443 Interface The SE050 supports in addition to the I2C interface ISO78161 and ISO14443-A Smartcard interfaces. For the ISO7816 interface SmartCard protocols T=0 and T=1 are supported. For the ISO14443 interface protocol T=CL is used. The supported resonance input capacitance is 56 pF. In addition one additional GPIO pad IO2 is supported. The RST_N pin can only be used as external reset source if the ISO7816 interface is enabled. If only the I2C interface is enabled the RST_N pad has no effect. If the SE050 is kept in reset state the current consumption is as defined for idle, see Table 12. 5 Power-saving modes The device provides two power-saving operation modes. The Power-down mode (with state retention) and the Deep Power-down mode (no state retention). These modes are activated via pad ENA (Deep Power-down mode) or by the SW (Power-down mode). 5.1 Power-down mode The Power-down mode has the following properties: • All internal clocks are frozen • CPU enters power-saving mode with program execution being stopped 1 ISO7816 is not enabled in generic SE050 configurations (see [4], AN12436) but available on customer request. SE050 All information provided in this document is subject to legal disclaimers. © 2022 NXP B.V. All rights reserved. Product data sheet Rev. 3.5 — 22 August 2022 504935 9 / 32 |
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