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PCF8576DH/2 Datasheet(PDF) 29 Page - NXP Semiconductors

Part # PCF8576DH/2
Description  Universal LCD driver for low multiplex rates
PDF  41 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PCF8576DH/2 Datasheet(HTML) 29 Page - NXP Semiconductors

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2004 Dec 22
29
Philips Semiconductors
Product specification
Universal LCD driver for low
multiplex rates
PCF8576D
11 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS =0V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
Notes
1. Typical output duty factor: 50% measured at the CLK output pin.
2. Not tested in production.
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
fCLK
oscillator frequency
note 1
960
1890
2640
Hz
tCLKH
input CLK HIGH time
60
−−µs
tCLKL
input CLK LOW time
60
−−µs
tPD(SYNC)
SYNC propagation delay
30
ns
tSYNCL
SYNC LOW time
1
−−µs
tPD(LCD)
driver delays with test loads
VLCD = 5 V; note 2
−−
30
µs
Timing characteristics: I2C-bus; note 3
fSCL
SCL clock frequency
−−
400
kHz
tBUF
bus free time between a STOP and START
1.3
−−µs
tHD;STA
START condition hold time
0.6
−−µs
tSU;STA
set-up time for a repeated START condition
0.6
−−µs
tLOW
SCL LOW time
1.3
−−µs
tHIGH
SCL HIGH time
0.6
−−µs
tr
SCL and SDA rise time
fSCL = 400 kHz
−−
0.3
µs
fSCL < 125 kHz
−−
1.0
µs
tf
SCL and SDA fall time
−−
0.3
µs
CB
capacitive bus line load
−−
400
pF
tSU;DAT
data set-up time
100
−−
ns
tHD;DAT
data hold time
0
−−
ns
tSU;STO
set-up time for STOP condition
0.6
−−µs
tSW
tolerable spike width on bus
−−
50
ns
handbook, full pagewidth
MCE439
3.3 k
1.5 k
0.5VDD
VDD
VSS
SDA,
SCL
CLK
1 nF
BP0 to BP3, and
S0 to S39
(2%)
(2%)
6.8
VDD
SYNC
(2%)
Fig.21 Test loads.



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