52
Preliminary
8-52
Military QuickRAM
Rev A
QL4016 Clock Cells
I/O Cell Input Delays
I/O Cell Output Delays
Notes:
[6] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25
°C.
Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as
specified in the Operating Range.
[8] The array distributed networks consist of 40 half columns and the global distributed networks consist of
44 half columns, each driven by an independent buffer. The number of half columns used does not
affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to
11 loads per half column.
[9] The following loads are used for tPXZ:
Symbol
Parameter
Propagation Delays (ns)
Loads per Half Column [8]
12348
10
11
tACK
Array Clock Delay
1.2
1.2
1.3
1.3
1.5
1.6
1.7
tGCKP
Global Clock Pin Delay
0.7
0.7
0.7
0.7
0.7
0.7
0.7
tGCKB
Global Clock Buffer Delay
0.8
0.8
0.9
0.9
1.1
1.2
1.3
Symbol
Parameter
Propagation Delays (ns)
Fanout [6]
12
3
4
8
10
tI/O
Input Delay (bidirectional pad)
1.3
1.6
1.8
2.1
3.1
3.6
TISU
Input Register Set-Up Time
3.1
3.1
3.1
3.1
3.1
3.1
TIH
Input Register Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
TlOCLK
Input Register Clock To Q
0.7
1.0
1.2
1.5
2.5
3.0
TlORST
Input Register Reset Delay
0.6
0.9
1.1
1.4
2.4
2.9
TlESU
Input Register clock Enable Set-Up Time
2.3
2.3
2.3
2.3
2.3
2.3
TlEH
Input Register Clock Enable Hold Time
0.0
0.0
0.0
0.0
0.0
0.0
Symbol
Parameter
Propagation Delays (ns)
Output Load Capacitance (pF)
30
50
75
100
150
TOUTLH
Output Delay Low to High
2.1
2.5
3.1
3.6
4.7
TOUTHL
Output Delay High to Low
2.2
2.6
3.2
3.7
4.8
TPZH
Output Delay Tri-state to High
1.2
1.7
2.2
2.8
3.9
TPZL
Output Delay Tri-state to Low
1.6
2.0
2.6
3.1
4.2
TPHZ
Output Delay High to Tri-State [9]
2.0
TPLZ
Output Delay Low to Tri-State [9]
1.2
5 pF
1K
Ω
5 pF
1K
Ω
tPHZ
tPLZ
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