UPSD3422EB40U6 datasheet(264/300 Pages) STMICROELECTRONICS

264 / 300 page

Obsolete

Product(s)

- Obsolete

Product(s)

Obsolete

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PSD module

UPSD3422, UPSD3433, UPSD3434, UPSD3454

264/300

28.6.9

JTAG security setting

A programmable security bit in the PSD module protects its contents from unauthorized

viewing and copying. The security bit is set by clicking on the “Additional PSD Settings” box

in the main flow diagram of PSDsoft Express, then choosing to set the security bit. Once a

file with this setting is programmed into a UPSD34xx using JTAG ISP, any further attempts

to communicate with the UPSD34xx using JTAG will be limited. Once secured, the only

JTAG operation allowed is a full-chip erase. No reading or modifying Flash memory or PLD

logic is allowed. Debugging operations to the MCU module are also not allowed. The only

way to defeat the security bit is to perform a JTAG ISP full-chip erase operation, after which

the device is blank and may be used again. The 8032 on the MCU module will always have

access to PSM Module memory contents through the 8-bit 8032 data bus connecting the

two die, even while the security bit is set.

28.6.10

Initial delivery state

When delivered from STMicroelectronics, UPSD34xx devices are erased, meaning all Flash

memory and PLD configuration bits are logic '1.' Firmware and PLD logic configuration must

be programmed at least the first time using JTAG ISP. Subsequent programming of Flash

memory may be performed using JTAG ISP, JTAG debugging, or the 8032 may run firmware

to program Flash memory (IAP).

Obsolete

Product(s)

- Obsolete

Product(s)

UPSD3422EB40U6 Datasheet(PDF) 264 Page - STMicroelectronics