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UPSD3422EB40U6 Datasheet(PDF) 282 Page - STMicroelectronics

Part # UPSD3422EB40U6
Description  Turbo Plus series Fast Turbo 8032 MCU with USB and programmable logic
PDF  300 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3422EB40U6 Datasheet(HTML) 282 Page - STMicroelectronics

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DC and AC parameters
UPSD3422, UPSD3433, UPSD3434, UPSD3454
282/300
Table 224.
CPLD macrocell asynchronous clock mode timing (5 V PSD module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
off
Slew
rate
Unit
fMAXA
Maximum frequency
external feedback
1/(tSA+tCOA)38.4
MHz
Maximum frequency
internal feedback (fCNTA)
1/(tSA+tCOA–10)
62.5
MHz
Maximum frequency
pipelined data
1/(tCHA+tCLA)71.4
MHz
tSA
Input setup time
7
+ 2
+ 10
ns
tHA
Input hold time
8
ns
tCHA
Clock input high time
9
+ 10
ns
tCLA
Clock input low time
9
+ 10
ns
tCOA
Clock to output delay
21
+ 10
– 2
ns
tARDA
CPLD array delay
Any macrocell
11
+ 2
ns
tMINA
Minimum clock period
1/fCNTA
16
ns
Table 225.
CPLD macrocell asynchronous clock mode timing (3 V PSD module)
Symbol
Parameter
Conditions
Min
Max
PT
Aloc
Turbo
off
Slew
rate
Unit
fMAXA
Maximum frequency
external feedback
1/(tSA+tCOA)
21.7
MHz
Maximum frequency
internal feedback
(fCNTA)
1/(tSA+tCOA–10)
27.8
MHz
Maximum frequency
pipelined data
1/(tCHA+tCLA)
33.3
MHz
tSA
Input setup time
10
+ 4
+ 15
ns
tHA
Input hold time
12
ns
tCHA
Clock high time
17
+ 15
ns
tCLA
Clock low time
13
+ 15
ns
tCOA
Clock to output delay
31
+ 15
– 6
ns
tARD
CPLD array delay
Any macrocell
20
+ 4
ns
tMINA
Minimum clock period
1/fCNTA
36
ns
Obsolete
Product(s)
- Obsolete
Product(s)



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