| Electronic Components Datasheet Search |
|
UPSD3422EB40U6 Datasheet(PDF) 280 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
UPSD3422EB40U6 Datasheet(HTML) 280 Page - STMicroelectronics |
|
280 / 300 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) DC and AC parameters UPSD3422, UPSD3433, UPSD3434, UPSD3454 280/300 Figure 101. Synchronous Clock mode timing – PLD Table 222. CPLD macrocell synchronous clock mode timing (5 V PSD module) Symbol Parameter Conditions Min Max PT Aloc Turbo Off Slew rate(1) 1. Fast slew rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. Unit fMAX Maximum frequency external feedback 1/(tS+tCO)40.0 MHz Maximum frequency internal feedback (fCNT) 1/(tS+tCO–10) 66.6 MHz Maximum frequency pipelined data 1/(tCH+tCL)83.3 MHz tS Input setup time 12 + 2 + 10 ns tH Input hold time 0 ns tCH Clock high time Clock input 6 ns tCL Clock low time Clock input 6 ns tCO Clock to output delay Clock input 13 – 2 ns tARD CPLD array delay Any macrocell 11 + 2 ns tMIN Minimum clock period(2) 2. CLKIN (PD1) tCLCL = tCH + tCL. tCH+tCL 12 ns tCH tCL tCO tH tS CLKIN INPUT REGISTERED OUTPUT AI02860 Obsolete Product(s) - Obsolete Product(s) |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |