CY7B995
Document #: 38-07337 Rev. *A
Page 2 of 11
Device Configuration
The outputs of the CY7B995 can be configured to run at
frequencies ranging from 6 MHz to 200 MHz. The feedback
input divider is controlled by the 3-level DS[0:1] pins as
indicated in Table 2 and the reference input divider is
controlled by the 3-level PD#/DIV pin as indicated in Table 1.
Notes:
1. ‘PD’ indicates an internal pull-down and ‘PU’ indicates an internal pull-up.
2. A bypass capacitor (0.1
µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their
high frequency filtering characteristic will be cancelled by the lead inductance of the traces.
3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections
remain in effect unless nF[1:0] = LL.
Pin Description
Pin
Name
I/O[1]
Type
Description
39
REF
I
LVTTL/LVCMOS
Reference Clock Input.
17
FB
I
LVTTL
Feedback Input.
37
TEST
I
3-Level
When MID or HIGH, disables PLL (except for conditions of note 3).
REF goes to all outputs. Set LOW for normal operation.
2
sOE#
I, PD LVTTL
Synchronous Output Enable. When HIGH, it stops clock outputs
(except 2Q0 and 2Q1) in a LOW state (for PE/HD = H or M) – 2Q0 and
2Q1 may be used as the feedback signal to maintain phase lock. When
TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output
disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW
for normal operation.
4
PE/HD
I, PU 3-Level
Selects Positive or Negative Edge Control and High or Low output
drive strength. When LOW / HIGH the outputs are synchronized with the
negative / positive edge of the reference clock, respectively. When at MID
level, the output drive strength is increased and the outputs synchronize
with the positive edge of the reference clock. Please see Table 9.
34, 33, 36, 35,
43, 42, 1, 44
nF[1:0]
I
3-Level
Select frequency and phase of the outputs. Please see Tables 3, 4, 5,
7, and 8.
41
FS
I
3-Level
Selects VCO operating frequency range. Please see Table 6.
26,27,20,21,
13,14,7,8
nQ[1:0]
O
LVTTL
Four banks of two outputs. Please see Table 5 for frequency settings.
32, 31
DS[1:0]
I
3-Level
Select feedback divider. Please see Table 2.
3
PD#/DIV
I, PU 3-Level
Power down and reference divider control. When LOW, shuts off entire
chip. When at MID level, enables the reference divider. Please see Table 1
for settings.
30
LOCK
O
LVTTL
PLL lock indication signal. HIGH indicates lock. LOW indicates that the
PLL is not locked and outputs may not be synchronized to the input.
5,6
VDDQ4[2] PWR Power
Power supply for Bank 4 output buffers. Please see Table 10 for supply
level constraints
15,16
VDDQ3 [2] PWR Power
Power supply for Bank 3 output buffers. Please see Table 10 for supply
level constraints
19,28,29
VDDQ1[2] PWR Power
Power supply for Bank 1 and Bank 2 output buffers. Please see
Table 10 for supply level constraints
18,40
VDD[2]
PWR Power
Power supply for the internal circuitry. Please see Table 10 for supply
level constraints
9-12, 22-25, 38 VSS
PWR Power
Ground.
Table 1. Reference Divider Settings
PD#/DIV
R–Reference Divider
H1
M2
L[4]
N/A
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