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PIC16LF1717TE/MLQTP Datasheet(PDF) 4 Page - Microchip Technology |
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PIC16LF1717TE/MLQTP Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 482 page ![]() TABLE 1: 28-PIN ALLOCATION TABLE (PIC16(L)F1718) RA0 2 27 AN0 CLCIN0 (1) IOC Y RA1 3 28 AN1 OPA1OUT CLCIN1 (1) IOC Y RA2 4 1 AN2 V - DAC1OUT1 IOC Y RA3 5 2 AN3 V + IOC Y RA4 6 3 OPA1IN+ T0CKI (1) IOC Y RA5 7 4 AN4 OPA1IN- DAC2OUT1 nSS (1) IOC Y RA6 10 7 IOC Y OSC2 CLKOUT RA7 9 6 IOC Y OSC1 CLKIN RB0 21 18 AN12 ZCD INT (1) IOC Y RB1 22 19 AN10 OPA2OUT IOC Y RB2 23 20 AN8 OPA2IN- IOC Y RB3 24 21 AN9 OPA2IN+ IOC Y RB4 25 22 AN11 IOC Y RB5 26 23 AN13 T1G (1) IOC Y RB6 27 24 CLCIN2 (1) IOC Y ICSPCLK RB7 28 25 DAC1OUT2 DAC2OUT2 CLCIN3 (1) IOC Y ICSPDAT T1CKI (1) SOSCO RC1 12 9 SOSCI IOC Y RC2 13 10 AN14 IOC Y RC3 14 11 AN15 SCK (1) IOC Y Note 1: Default peripheral input. Alternate pins can be selected as the peripheral input with the PPS input selection registers. 2: All pin digital outputs default to PORT latch data. Alternate outputs can be selected as the peripheral digital output with the PPS output selection registers. 3: These peripheral functions are bidirectional. The output pin selections must be the same as the input pin selections. 4: Alternate outputs are excluded from solid shaded areas. 5: Alternate inputs are excluded from dot shaded areas. C1IN1+ C1IN0- C2IN0- C1IN1- C2IN1- C1IN0+ C2IN0+ C2IN1+ COG1IN (1) C1IN3- C2IN3- C1IN2- C2IN2- RC0 11 8 IOC Y CCP2 (1) CCP1 (1) |
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