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PIC16LF1717TE/MLQTP Datasheet(PDF) 52 Page - Microchip Technology |
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PIC16LF1717TE/MLQTP Datasheet(HTML) 52 Page - Microchip Technology |
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52 / 482 page  PIC16(L)F1717/8/9 DS40001740D-page 52 2014-2020 Microchip Technology Inc. FIGURE 3-8: ACCESSING THE STACK EXAMPLE 4 3.6.2 OVERFLOW/UNDERFLOW RESET If the STVREN bit in Configuration Words is programmed to ‘1’, the device will be reset if the stack is PUSHed beyond the sixteenth level or POPed beyond the first level, setting the appropriate bits (STKOVF or STKUNF, respectively) in the PCON register. 3.7 Indirect Addressing The INDFn registers are not physical registers. Any instruction that accesses an INDFn register actually accesses the register at the address specified by the File Select Registers (FSR). If the FSRn address specifies one of the two INDFn registers, the read will return ‘0’ and the write will not occur (though Status bits may be affected). The FSRn register value is created by the pair FSRnH and FSRnL. The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 Return Address 0x00 STKPTR = 0x10 When the stack is full,the nextCALL or an interruptwillsetthe Stack Pointerto 0x10.This is identicalto address 0x00 so the stack willwrap and overwrite the return address at0x00.Ifthe Stack Overflow /Underflow Resetis enabled,a Resetwilloccurand location 0x00 will notbe overwritten. Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address Return Address TO SH :TO SL |
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