STW5093 datasheet(10/34 Pages) STMICROELECTRONICS

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STw5093

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Table 2. Control Register CR0 Functions

state at power on initialization

(1):

significant in companded mode only

Table 3. Control Register CR1 Functions

state at power on initialization

(1):

significant in companded mode only

reserved: write 0

543

Function

MCLK or AUXCLK = 512 kHz

MCLK or AUXCLK = 1.536 MHz

MCLK or AUXCLK = 2.048 MHz

MCLK or AUXCLK = 2.560 MHz

Linear code

Companded code

Linear Code

Companed Code

2-complement

sign and magnitude

2-complement

1-complement

MU-law: CCITT D3-D4

MU-law: Bare Coding

A-law including even bit inversion

A-law: Bare Coding

B1 and B2 consecutive

(1)

B1 and B2 separated

(1)

8 bits time-slot

(1)

7 bits time-slot

(1)

Normal operation

Digital Loop-back

Function

DM1

DM0

SLC

delayed data timing

non-delayed normal data timing

non-delayed reverse data timing

L0 latch set to 1

L0 latch set to 0

DR connected to rec. path

CR2 connected to rec. path

(1)

Trans path connected to DX

CR3 connected to DX

(1)

voice data transfer disable

voice data transfer enable

B1 channel selected

B2 channel selected

(1)

MCLK Master Clock and FS Frame Sync inputs are selected *

AUXCLK Auxiliary Clock input is selected

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