M95128-R datasheet(23/48 Pages) STMICROELECTRONICS

Part #	M95128-R

Description	128-Kbit serial SPI bus EEPROM with high-speed clock

PDF	48 Pages

Scroll/Zoom	100%

Manufacturer	STMICROELECTRONICS [STMicroelectronics]

Direct Link	http://www.st.com

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23 / 48 page

Power-up and delivery state

7.1

Power-up state

After power-up, the device is in the following state:

•

Standby power mode

•

deselected (after power-up, a falling edge is required on Chip select (S) before any instructions can be

started)

•

not in the Hold condition

•

the Write enable latch (WEL) is reset to 0

•

Write in progress (WIP) is reset to 0.

The SRWD, BP1 and BP0 bits of the Status register are unchanged from the previous power-down (they are non-

volatile bits).

7.2

Initial delivery state

The device is delivered with the memory array and Identification page bits set to all 1s (each byte = FFh). The

Status register Write Disable (SRWD) and Block protect (BP1 and BP0) bits are initialized to 0.

M95128-W M95128-R M95128-DF

Power-up and delivery state

DS1356 - Rev 20

page 23/48

M95128-R Datasheet(PDF) 23 Page - STMicroelectronics