is within its valid operating range. However, many applications benefit from the use of an enable divider network

as shown in Figure 8-1, which establishes a precision input undervoltage lockout (UVLO). This can be used for

sequencing, to prevent re-triggering the device when used with long input cables, or to reduce the occurrence of

deep discharge of a battery power source. An external logic signal can also be used to drive the enable input to

toggle the output on and off and for system sequencing or protection.

Calculate RENB using Equation 6:

RENBkΩ =RENTkΩ × VEN_RISE V

VINon V−VEN_RISE V

(6)

where

• A typical value for RENT is 100 kΩ.

• VEN_RISE is enable rising threshold voltage of 1.263 V (typical).

• VIN(on) is the desired start-up input voltage.

8.3.7 Power-Good Monitor (PG)

The TLVM13610 provides a power-good status signal to indicate when the output voltage is within a regulation

window of 94% to 112%. The PG voltage goes low when the feedback (FB) voltage is outside of the specified

PGOOD thresholds (see Figure 7-7). This action can occur during current limit and thermal shutdown, as well as

when disabled and during start-up.

PG is an open-drain output, requiring an external pullup resistor to a DC supply, such as VCC or VOUT. To limit

current supplied by VCC, the recommended range of pullup resistance is 20 kΩ to 100 kΩ. A 26-µs deglitch filter

prevents false flag operation for short excursions of the output voltage, such as during line and load transients.

When EN is pulled low, PG is forced low and remains remains valid as long as the input voltage is above 1 V

(typical). Use the PG signal for start-up sequencing of downstream regulators, as shown in Figure 8-2, or for

fault protection and output monitoring.

8

FB

17 EN

RUV1

1 M

VOUT1 = 5 V

RFB1

RFB2

40.2 k

10 k

1 V

8

FB

17

RPG

100 k

RFB3

RFB4

23.2 k

10 k

1 V

VOUT2 = 3.3 V

VIN(on) = 13.9 V

VIN(off) = 10 V

Regulator #1

Start-up based on

input voltage UVLO

Regulator #2

Sequential start-up

based on PG

PG 13

PG 13

RUV2

100 k

EN

Figure 8-2. TLVM13610 Sequencing Implementation Using PG and EN

8.3.8 Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)

Adjust the switch-node slew rate of the TLVM13610 to slow the switch-node voltage rise time and improve EMI

performance at high frequencies. However, slowing the rise time decreases efficiency. Care must be taken to

balance the improved EMI versus the decreased efficiency.

Place a resistor from RBOOT and CBOOT to allow adjustment of the internal resistance to balance EMI and

efficiency performance. If improved EMI is not required, connect RBOOT to CBOOT to short the internal resistor,

thus resulting in highest efficiency. If lower EMI is required, connect a resistor from 100 Ω - 500 Ω to. Floating

the RBOOT pin results in 20-ns rise time and is not recommended due to increased power loss for higher load

currents.

TLVM13610

SLVSH63 – FEBRUARY 2023

www.ti.com

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