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82V3155 Datasheet(PDF) 13 Page - Renesas Technology Corp |
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82V3155 Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 35 page ![]() Functional Description 13 January 11, 2017 82V3155 ENHANCED T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS When the IDT82V3155 primarily enters the Holdover mode for a short time period and then returns back to the Normal mode, the TIE Control Circuit should not be enabled. This will prevent undesired accumulated phase change between the input and output. If the TIE Control Block is disabled manually or automatically, a reference switch will result in a phase alignment between the input signal and the output signal as shown in Figure - 6. The slope of the phase adjustment is limited to 5 ns per 125 µs. Figure - 5 Reference Switch with TIE Control Block Enabled Figure - 6 Reference Switch with TIE Control Block Disabled Input Clock Ref1 Ref2 Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 s Output Clock Input Clock Ref1 Ref2 Time = 0.00 s Time = 0.25 s Time = 0.50 s Time = 0.75 s Time = 1.0 s Time = 1.25 s Time = 1.50 s Time = 1.75 s Output Clock |
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