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VN9D5D20FN Datasheet(PDF) 39 Page - STMicroelectronics |
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VN9D5D20FN Datasheet(HTML) 39 Page - STMicroelectronics |
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39 / 96 page ![]() SOCR Channel control register 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R RW RW RW RW R R R R R R RW R Address: 0x13h Type: RW Reset: 0 Description: The SOCR register is used to turn ON/OFF the related channel. The WDTB bit that must be toggled within tWDBT (watchdog timeout) to avoid entering in fail-safe mode. This bit is already present in the output control register and it is duplicated in the SOCR register to simplify the SPI usage. [15:12] RESERVED [11] SOCR3 bit controls output state of channel 3 1 - output enabled 0 - output disabled [10] SOCR2 bit controls output state of channel 2 1 - output enabled 0 - output disabled [9] SOCR1 bit controls output state of channel 1 1 - output enabled 0 - output disabled [8] SOCR0 bit controls output state of channel 0 1 - output enabled 0 - output disabled [7:2] RESERVED [1] Watchdog toggle bit [0] PARITY: parity bit VN9D5D20FN Control registers DS13579 - Rev 7 page 39/96 |
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