9LRS3165B

IDT®

64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor

1533B—01/06/15

64-pin CK505 Compatible Clock w/Fully Integrated Voltage

Regulator + Integrated Series Resistor

1

DATASHEET

Pin Configuration

Recommended Application:

CK505 compatible clock with fully integrated voltage regulator and

Internal series resistor on differential outputs

Output Features:

•

2 - CPU differential low power push-pull pairs

•

9 - SRC differential low power push-pull pairs

•

1 - CPU/SRC selectable differential low power push-pull pair

•

1 - SRC/DOT selectable differential low power push-pull pair

•

5 - PCI, 33MHz

•

1 - PCI_F, 33MHz free running

•

1 - USB, 48MHz

•

1 - REF, 14.318MHz

Key Specifications:

•

CPU outputs cycle-cycle jitter < 85ps

•

SRC output cycle-cycle jitter < 125ps

•

PCI outputs cycle-cycle jitter < 250ps

•

+/- 100ppm frequency accuracy on CPU & SRC clocks

Features/Benefits:

•

Does not require external pass transistor for voltage regulator

•

Integrated 33ohm series resistors on differential outputs,

Zo=50

Ω

•

Supports spread spectrum modulation, default is 0.5% down

spread

•

Uses external 14.318MHz crystal, external crystal load caps

are required for frequency tuning

•

Selectable between one SRC differential push-pull pair and

two single-ended outputs

•

Meets PCIEX Gen2 specification on dedicated SRC outputs.

Muxed SRC outputs meet PCIEX Gen1 specification, except

SRC1.

•

Single-ended programmable slew rate control for RFI

reduction

•

Meets PCIEX <85ps cycle-to-cycle jitter for SRC[11:1]

FSLC

2

B0b7

FSLB

1

B0b6

FSLA

1

B0b5

CPU

MHz

SRC

MHz

PCI

MHz

REF

MHz

USB

MHz

DOT

MHz

0

0

0

266.66

0

0

1

133.33

0

1

0

200.00

0

1

1

166.66

1

0

0

333.33

1

0

1

100.00

1

1

0

400.00

11

1

1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in

the Input/Supply/Common Output Parameters Table for correct values.

Also refer to the Test Clarification Table.

2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS

specifications in the Input/Supply/Common Output Parameters Table for correct values.

48.00

Reserved

Table 1: CPU Frequency Select Table

96.00

100.00

33.33

14.318

PCI0/CR#_A 1

64 SCLK

VDDPCI 2

63 SDATA

PCI1/CR#_B 3

62 REF/FSLC/TEST_SEL

PCI2/TME 4

61 VDDREF

PCI3 5

60 X1

PCI4/27_SEL 6

59 X2

PCI5_F/ITP_EN 7

58 GNDREF

GNDPCI 8

57 FSLB/TEST_MODE

VDD48 9

56 CK_PWRGD/PD#

USB48M/FSLA 10

55 VDDCPU

GND48 11

54 CPUT_LR0

VDDI/O96MHz 12

53 CPUC_LR0

DOT96T/SRCT_LR0 13

52 GNDCPU

DOT96C/SRCC_LR0 14

51 CPUT_F_LR1

GND 15

50 CPUC_F_LR1

VDD 16

49 VDDCPU_IO

27FIX/LCDT/SRCT_LR1/SE1 17

48 NC

27SS/LCDC/SRCC_LR1/SE2 18

47 CPUT_ITP_LR2/SRCT8

GND 19

46 CPUC_ITP_LR2/SRCC8

VDDPLL3I/O 20

45 VDDSRCI/O

SRCT_LR2/SATACLKT 21

44 SRCT_LR7/CR#_F

SRCC_LR2/SATACLKC 22

43 SRCC_LR7/CR#_E

GNDSRC 23

42 GNDSRC

SRCT_LR3/CR#_C 24

41 SRCT_LR6

SRCC_LR3/CR#_D 25

40 SRCC_LR6

VDDSRCI/O 26

39 VDDSRC

SRCT_LR4 27

38 PCI_STOP#

SRCC_LR4 28

37 CPU_STOP#

GNDSRC 29

36 VDDSRCI/O

SRCT_LR9 30

35 SRCC_LR10

SRCC_LR9 31

34 SRCT_LR10

SRCC_LR11/CR#_G 32

33 SRCT_LR11/CR#_H

64-TSSOP