IDT®

64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor

1533B—01/06/15

9LRS3165B

64-pin CK505 Compatible Clock w/Fully Integrated Voltage Regulator + Integrated Series Resistor

14

Electrical Characteristics - Differential Jitter Parameters

PARAMETER

Symbol

Conditions

Min

TYP

Max

Units

Notes

t

jphasePLL

PCIe Gen 1

86

ps (p-p)

1,11

t

jphaseLo

PCIe Gen 2

10kHz < f < 1.5MHz

3

ps

(RMS)

1,11

t

jphaseHigh

PCIe Gen 2

1.5MHz < f < Nyquist (50MHz)

3.1

ps

(RMS)

1,11

*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, Rs= 0Ω, CL = 2pF

Notes on Electrical Characteristics:

1Guaranteed by design and characterization, not 100% tested in production.

2 Slew rate measured through Vswing centered around differential zero

3 Vxabs is defined as the voltage where CLK = CLK#

4 Only applies to the differential rising edge (CLK rising and CLK# falling)

6 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz

10 At nominal voltage and temperature

9 See PCI Clock-to-Clock Delay Figure

7 Operation under these conditions is neither implied, nor guaranteed.

8 Maximum input voltage is not to exceed maximum VDD

Jitter, Phase

5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK

and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.