ASI4U datasheet(13/71 Pages) RENESAS

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ASI4U / ASI4U-E / ASI4U-F Datasheet

January 26, 2016

After power-on reset, the IC is set to 16.000 MHz operation by default. After approximately

200µs, it will either switch to 8.000 MHz operation or remain in the 16.000 MHz mode. The

frequency detection is active until the first AS-i telegram has been successfully received in order

to ensure that the IC has found the correct clock frequency setting. The detection result is locked

thereafter to increase resistance against burst or other interferences.

The oscillator unit also contains a clock watchdog circuit that can generate an unconditional IC

reset if there has been no clock oscillation for more than approximately 20µs. This is to prevent

the IC from unpredictable behavior if a clock signal is no longer available.

THERMAL/OVERLOAD PROTECTION The IC is self-protected against overheating and short-circuiting of

the UOUT pin toward IC ground.

If the silicon die temperature rises above approximately 140°C for more than 2 seconds, the IC

detects overheating, switches off the electronic inductor, performs an IC reset, and sets all analog

blocks to power down mode. Although the 5V regulator is turned off in this state, there will still

remain a voltage of approximately 3V to 3.5V available at U5R that is derived from the internal

start circuitry. The overheating protection state can only be de-activated by power-cycling the

AS-i voltage.

Short-circuiting the UOUT pin toward IC ground causes the same IC behavior as overheating.

IRD CMOS / AC CURRENT INPUT The IRD pin is the input for the additional addressing channel in Slave

Mode (see section 3.2 for a description of general IC operational modes) or the direct AS-i

transmitter input in Master Mode. In Slave Mode, the IRD pin can be operated either in CMOS

Mode or AC Current Input Mode. The latter is provided for direct connection of a photodiode.

More detailed information can be found in section 4.3.

FID DIGITAL / ANALOG STAGE The FID pin can be set to the Digital CMOS Mode or Analog Voltage Input

Mode. In Slave Mode, it is set to CMOS operation; in Master Mode, it works in Analog Mode and

functions as the input for the power fail comparator.

INPUT STAGE All digital inputs, except the oscillator pins, have high voltage capabilities and partial Schmitt

trigger and pull-up features. For more details, see section 4.4.

OUTPUT STAGE All digital output stages, except for the oscillator pins, have high voltage capabilities and are

implemented as NMOS open-drain buffers. Each pin can sink up to 10mA of current.

3.2. General Operational Modes

The ASI4U/ ASI4U-E/ASI4U-F provides two main operational modes and two additional sub-operational modes.

The two main operation modes are Slave Mode and Master Mode. Sub-operation modes are Repeater Mode and

Monitor Mode. The latter were derived from Master Mode for providing different output signals at the Parameter

Port.

The active operational mode is selected by programming the Master_Mode and Repeater_Mode flags in the

“Firmware Area” block of the EEPROM (also see Table 3.4). The EEPROM is read at every initialization of the IC.

Online mode switching is not provided. Table 3.1 gives the bit configurations for the operational modes.

ASI4U Datasheet(PDF) 13 Page - Renesas Technology Corp