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AX88871AP Datasheet(PDF) 6 Page - ASIX Electronics Corporation |
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AX88871AP Datasheet(HTML) 6 Page - ASIX Electronics Corporation |
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6 / 30 page  AX88871AP Bripeater ASIX ELECTRONICS CORPORATION 6 1.3 Block Diagram 10/100 Q-PHY 10/100 Q-PHY MII I/F MII interface Re-concilia- tion Sub-layer (Port 1 - Port 7 ) Speed Detection circuit Elasticity Buffer for 100Mbps and 10Mbps MUX Repeater State Machine of 100Mbps Collision Handling Logic for 100Mbps and10Mbps Per port Jabber ctl, auto-partition SM & Per port Collision , Partition counters. Registers MIB I/F (Reserved) Cascade Arbitration Logic of 100Mbps MII I/F Repeater State Machine of 10Mbps 100Mbps to 10Mbps Bridge (Reserved) Fig - 1 Chip Block Diagram |
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