83052I Data Sheet

©2015 Integrated Device Technology, Inc

December 15, 2015

2

TABLE 1. PIN DESCRIPTIONS

TABLE 2. PIN CHARACTERISTICS

TABLE 3. CONTROL INPUT FUNCTION TABLE

Number

Name

Type

Description

1V

DDO

Power

Output supply pin.

2

GND

Power

Power supply ground.

3, 6

CLK1, CLK0

Input

Pulldown Single-ended clock inputs. LVCMOS/LVTTL interface levels.

4V

DD

Power

Positive supply pin.

5

OE

Input

Pullup

Output enable. When LOW, outputs are in HIGH impedance state.

When HIGH, outputs are active. LVCMOS / LVTTL interface levels.

7

SEL0

Input

Pulldown

Clock select input. See Table 3. Control Input Function Table.

LVCMOS / LVTTL interface levels.

8

Q

Output

Single-ended clock output. LVCMOS/LVTTL interface levels.

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

C

IN

Input Capacitance

4

pF

R

PULLUP

Input Pullup Resistor

51

k

Ω

R

PULLDOWN

Input Pulldown Resistor

51

k

Ω

C

PD

Power Dissipation Capacitance

(per output)

V

DDO

= 3.465V

18

pF

V

DDO

= 2.625V

19

pF

V

DDO

= 1.89V

19

pF

R

OUT

Output Impedance

15

Ω

Control Inputs

Input Selected to Q

SEL0

0

CLK0

1

CLK1