85411I Data Sheet

©2016 Integrated Device Technology, Inc

Revision B January 20, 2016

8

APPLICATION INFORMATION

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = V

DD

/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input clock

swing is only 2.5V and V

DD

= 3.3V, V_REF should be 1.25V and R2/

R1 = 0.609.

RECOMMENDATIONS FOR UNUSED OUTPUT PINS

OUTPUTS:

LVDS

All unused LVDS output pairs can be either left floating or

terminated with 100

Ω across. If they are left floating, there

should be no trace attached.