DS2790 Programmable 1-Cell Li-Ion Fuel Gauge and Protector

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SYSTEM INTERRUPTS

Multiple interrupt sources are available for quick response to internal and external events. The MAXQ20

architecture uses a single interrupt vector (IV), single interrupt-service routine (ISR) design. For maximum flexibility,

interrupts can be enabled globally, individually, or by module. When an interrupt condition occurs, its individual flag

is set, even if the interrupt source is disabled at the local, module, or global level. Interrupt flags must be cleared

within the firmware-interrupt routine to avoid repeated interrupts from the same source. Application software must

ensure a delay between the write to the flag and the RETI instruction to allow time for the interrupt hardware to

remove the internal interrupt condition. Asynchronous interrupt flags require a one-instruction delay and

synchronous interrupt flags require a two-instruction delay.

When an enabled interrupt is detected, execution jumps to a user-programmable interrupt vector location. The IV

register defaults to 0000h on reset or power-up, so if it is not changed to a different address, application firmware

must determine whether a jump to 0000h came from a reset or interrupt source.

Once control has been transferred to the ISR, the interrupt identification register (IIR) can be used to determine if a

system register or peripheral register was the source of the interrupt. The specified module can then be

interrogated for the specific interrupt source and software can take appropriate action. Interrupts are evaluated by

application code allowing the definition of a unique interrupt priority scheme for each application. Interrupt sources

are available from the Watchdog timer described in the MAXQ users guide, the TWSINT Register described in the

2-Wire Interface section, and the EINT Register as shown in Figure 6.

EINT Register

The EINT Register contains interrupts generated by the ADC, the timer-counter, the protection circuits, the general

purpose port pins and the serial-interface port pins. Their masks and their configuration bits, along with the

RST pin

status and control, are present in the EIC and PAF registers of module 0.