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RAA271000 Datasheet(PDF) 21 Page - Renesas Technology Corp |
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RAA271000 Datasheet(HTML) 21 Page - Renesas Technology Corp |
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21 / 105 page ![]() R16DS0051EU0101 Rev.1.01 Page 21 May 23, 2022 RAA271000 Datasheet 6.1.2 SPI Configuration The following register bits configure the SPI operation: ▪ IO_SPICPOL: SPI clock polarity, RAA271000 is configured as active high, IO_SPICPOL = 0. ▪ IO_SPICPHA: SPI clock phase, RAA271000 samples data on rising edge of SPI clock, IO_SPICPHA = 0. The four possible modes of clocking are shown in Figure 15. ▪ IO_SPIRWPOL: R/W bit polarity, RAA271000 SPI_RWPOL is set to 0, 1: Read, 0: Write. ▪ IO_SPIMODE: Packet length enable. The RAA271000 uses packet length mode by default, which means, the third data byte from master is the packet length and indicates the total number of data words to be sent/received in a burst transaction. Figure 15. Four Possible Clocking Modes Table 5. SPI_RWPOL R/W Bit Settings SPI_RWPOL R/W Operation 00 Write 0 1 Read SS_B SPI_CLK:IO_SPICPOL = 0 SPI_CLK:IO_SPICPOL = 1 MISO:IO_SPIPCPHA = 0 MOSI:IO_SPIPCPHA = 0 MISO:IO_SPIPCPHA = 1 MOSI:IO_SPIPCPHA = 1 |
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