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DA7280 Datasheet(PDF) 13 Page - Renesas Technology Corp |
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DA7280 Datasheet(HTML) 13 Page - Renesas Technology Corp |
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13 / 80 page  DA7280-Automotive Wideband LRA/ERM Haptic Driver for Automotive Applications Datasheet Revision 1.4 01-Mar-2022 CFR0011-120-00 13 of 79 © 2022 Renesas Electronics 4.4 Timing Characteristics Unless otherwise noted, the parameters listed in Table 8 are valid for TA = 25°C, VDD = 3.8 V, and VDDIO = 1.8 V. Table 8: Timing Characteristics Parameter Description Conditions Min Typ Max Unit tON Cold boot to IDLE state time VDD present and PoR released 1.2 1.5 ms tOUT_IDLE Time to output from IDLE state From GPI or I2C trigger to output drive 0.7 5 ms tOUT_STANDB Y Time to output from STANDBY state From GPI or I2C trigger to output drive 0.1 5 ms STOP SDA SCL tFALL tRISE tFALL START tHOLD_START tHOLD_DATA 1/fSCL 70% 30% 70% 30% tSETUP_DATA tLO_SCL tHI_SCL tDATA ACK tDATA_ACK tSETUP_STOP tSETUP_START Figure 4: I2C Interface Timing Table 9: I2C Interface Timing Requirements Parameter Description Conditions Min Max Unit tBUF Bus free time from STOP to START condition 0.5 µs Standard, Fast, and Fast-Plus Modes CBUS Bus line capacitive load 520 pF fSCL SCL clock frequency 0 1000 (Note 1) kHz tSETUP_START Start condition setup time 0.26 µs tHOLD_START Start condition hold time 0.26 µs tLO_SCL SCL low time 0.5 µs tHI_SCL SCL high time 0.26 µs tRISE SCL and SDA rise time 120 ns tFALL SCL and SDA fall time 120 ns tSETUP_DATA Data setup time 50 ns tHOLD_DATA Data hold-time 0 ns tSETUP_STOP Stop condition setup time 0.26 µs tDATA Data valid time 0.45 µs tDATA_ACK Data valid acknowledge time 0.45 µs tSPIKE Spike suppression (SCL, SDA) Fast/Fast+ mode 50 ns Note 1 fSCL maximum is 400 kHz at VDDIO ≤ 1.65 V and 1000 kHz at VDDIO > 1.65 V. |
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