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DA7281 Datasheet(PDF) 61 Page - Renesas Technology Corp

Part # DA7281
Description  LRA/ERM Haptic Driver with Multiple I²C Addresses, Integrated Waveform Memory, and Wideband Support
PDF  88 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA7281 Datasheet(HTML) 61 Page - Renesas Technology Corp

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DA7281
LRA/ERM Haptic Driver with Multiple I²C
Addresses, Integrated Waveform Memory, and
Wideband Support
Datasheet
Revision 3.1
10-Feb-2022
CFR0011-120-00
61 of 87
© 2022 Renesas Electronics
S SLAVEaddr W A
REG addr
A
SLAVEaddr
A
S = START condition
A = Acknowledge (low)
Sr = Repeat START condition
A
* = Not Acknowledge (NAK)
P = STOP condition
W = Write (low)
R = Read (high)
Master to Slave
Slave to Master
7-bits
1 bit
8-bits
7-bits
DATA
A
Sr
R
1-bit
8-bits
S
SLAVEaddr W
A
REG addr
A
SLAVEaddr
A
7-bits
1-bit
8-bits
7-bits
DATA
P
S
R
1-bit
8-bits
P
A
A
*
P
DATA
DATA
A
A
*
DATA
8-bits
8-bits
8-bits
Figure 37: Examples of I2C Page Read (SDA line)
In Page mode the slave address after Sr (Repeated START condition) must be the same as the
previous slave address.
Consecutive (Page) Write mode, I2C_WR_MODE = 0, is supported if the master sends several data
bytes following a slave register address. The I2C control block then increments the address pointer to
the next I2C address, stores the received data and sends an Acknowledge until the master sends the
STOP condition.
S SLAVEaddr W A
REGadr
A
DATA
A
S = START condition
A = Acknowledge (low)
Sr = Repeat START condition
A
* = Not Acknowledge (NAK)
P = STOP condition
W = Write (low)
R = Read (high)
Master to Slave
Slave to Master
7-bits
1 bit
8-bits
8-bits
DATA
A
1-bit
8-bits
A
P
DATA
……….
A
8-bits
Repeated writes
Figure 38: I2C Page Write (SDA line)
An alternative Repeated-Write mode that uses non-consecutive slave register addresses is available
using the CIF_I2C1 register. In this Repeat Mode, I2C_WR_MODE = 1, the slave can be configured
to support a
host’s repeated write operations into several non-consecutive registers. Data is stored at
the previously received register address. If a new START or STOP condition occurs within a
message, the bus returns to Idle mode. This is illustrated in Figure 39.
S SLAVEaddr W A
REG addr
A
DATA
A
S = START condition
A = Acknowledge (low)
Sr = Repeat START condition
A
* = Not Acknowledge (NAK)
P = STOP condition
W = Write (low)
R = Read (high)
Master to Slave
Slave to Master
7-bits
1 bit
8-bits
8-bits
REG addr
A
1-bit
8-bits
A
P
DATA
……….
A
8-bits
Repeated writes
Figure 39: I2C Repeated Write (SDA line)
In Page mode, I2C_WR_MODE = 0, both Page mode reads and writes using auto-incremented
addresses, and Repeat mode reads and writes using non auto-incremented addresses, are
supported. In Repeat mode, I2C_WR_MODE = 1, however, only Repeat mode reads and writes are
supported.



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