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DA7280-00FVC Datasheet(PDF) 39 Page - Renesas Technology Corp |
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DA7280-00FVC Datasheet(HTML) 39 Page - Renesas Technology Corp |
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39 / 85 page ![]() DA7280 LRA/ERM Haptic Driver with Multiple Input Triggers, Integrated Waveform Memory and Wideband Support Datasheet Revision 3.2 02-Mar-2022 CFR0011-120-00 39 of 84 © 2022 Renesas Electronics Table 14: Default CUSTOM_WAVE_GEN_COEFFx Settings Point % of IMAX[4:0] Corresponding Bits 0 0 - 1 37.9 CUSTOM_WAVE_GEN_COEFF1 2 70.3 CUSTOM_WAVE_GEN_COEFF2 3 92.2 CUSTOM_WAVE_GEN_COEFF3 4 100 - Configure the following bits to enable custom waveform operation: ● BEMF_SENSE_EN = 0 ● WAVEGEN_MODE = 1 ● V2I_FACTOR_FREEZE = 1 ● DELAY_H = 0 ● DELAY_SHIFT_L = 0 ● DELAY_FREEZE = 1 ● ACCELERATION_EN = 0 ● RAPID_STOP_EN = 0 ● AMP_PID_EN = 0 After the above setup is executed, amplitude data can be streamed in any mode, see Section 5.6.5, and output frequency can be updated, see Section 5.7.6. 5.7.7 Embedded Operation Should DA7280 be required to operate in a setup where no host is present or due to software limitations unable to communicate with the device during its required operation, DA7280 can operate in embedded operation by setting EMBEDDED_MODE = 1. In this case DA7280 is configured to clear all system faults as it enters inactive mode when playback is finished or if a fault has been detected, see Section 5.6.6. For example, if a short circuit occurs, the system will react in its usual way: stop driving, disable the current loop, and go to Inactive mode. Once in Inactive mode, the generated interrupt is automatically cleared and DA7280 will attempt to drive again on the next playback request without the host having to come in and clear faults. 5.7.8 Polarity Change Reporting for Half-Period Control in DRO Mode For advanced sequence playback in DRO mode, the host may require DA7280 to update the output drive amplitude every half period. Since the I2C clock is asynchronous to the DA7280 internal clock and the exact timing of the half-period will change dynamically based on the frequency tracking loop, this is not a trivial operation. To overcome this limitation, the register POLARITY provides feedback. POLARITY toggles at the start of every half-period (so at a rate of 400 Hz for a 200 Hz resonant frequency actuator). This allows software synchronization of the updates to the OVERRIDE_VAL, see Figure 19. |
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