Datasheet

4-Feb-2022

CFR0011-120-01

Revision 1.04

Page 11 of 18

SLG59M1735C

A 10.5 mΩ, 4 A Load Switch

with Soft-start and Protection Features in WLCSP

©2022 Renesas Electronics Corporation

Layout Guidelines:

1. The VDD pin (A1) needs a 0.1µF (or larger) external capacitor to smooth pulses from the power supply. Locate this capacitor

as close as possible to the SLG59M1735C's A1 pin.

2. Since the VIN and VOUT pins dissipate most of the heat generated during high-load current operation, it is highly recommended

to make power traces as short, direct, and wide as possible. A good practice is to make power traces with absolute minimum

widths of 15 mils (0.381 mm) per Ampere. A representative layout, shown in Figure 5, illustrates proper techniques for heat to

transfer as efficiently as possible out of the device;

3. To minimize the effects of parasitic trace inductance on normal operation, it is recommended to connect input CIN and output

CLOAD low-ESR capacitors as close as possible to the SLG59M1735C's VIN and VOUT pins;

4. The GND pin should be connected to system analog or power ground plane.

SLG59M1735C Evaluation Board:

А GreenFET Evaluation Board for SLG59M1735C is designed according to the statements above and is illustrated on Figure 5.

Please note that evaluation board has D_Sense and S_Sense pads. They cannot carry high currents and dedicated only for

RDSON evaluation.

Figure 5. SLG59M1735C Evaluation Board