HMP8117 datasheet(39/45 Pages) RENESAS

39 / 45 page

HMP8117

FN4643 Rev 4.00

Page 39 of 45

July 29, 2009

LCAP

0.1µF

to AGND

Storage capacitor for Luminance signal DC restoration. The LCAP voltage offsets the sync

tip to the lower reference of the A/D. A 0.1

F capacitor should be connected between this

pin and AGND. This capacitor should be as close to this pin as possible for best

performance.

CCAP

0.1µF

to AGND

Storage capacitor for Chrominance signal DC restoration. The CCAP voltage offsets the

chroma signal to mid-range of the A/D. A 0.1

F capacitor should be connected between

this pin and AGND. This capacitor should be as close to this pin as possible for best

performance.

P0-P15

42, 43, 45,

47-51, 54-58,

60, 63, 64

ON/A

Pixel output pins. See Table 3. These pins are three-stated after a RESET or software reset.

HSYNC

10k

 Pullup

Horizontal sync output. HSYNC is asserted during the horizontal sync intervals. The

polarity of HSYNC is programmable. This pin is three-stated after a RESET or software

reset and should be pulled high through a 10k

 resistor.

VSYNC

10k

 Pullup

Vertical sync output. VSYNC is asserted during the vertical sync intervals. The polarity of

VSYNC is programmable. This pin is three-stated after a RESET or software reset and

should be pulled high through a 10k

 resistor.

FIELD

10k

 Pullup

FIELD output. The polarity of FIELD is programmable. This pin is three-stated after a

RESET or software reset and should be pulled high through a 10k

 resistor.

DVALID

10k

 Pullup

Data valid output. DVALID is asserted during CLK2 cycles that contain valid pixel data. This

pin is three-stated after a RESET or software reset and should be pulled high through a

10k

 resistor.

BLANK

10k

 Pullup

Composite blanking output. BLANK is asserted during the horizontal and vertical blanking

intervals. The polarity of BLANK is programmable. This pin is three-stated after a RESET

or software reset and should be pulled high through a 10k

 resistor.

VBIVALID

10k

 Pullup

Vertical Blanking Interval Valid output. VBIVALID is asserted during CLK2 cycles that

contain valid VBI (Vertical Blanking Interval) data such as Closed Captioning, Teletext, and

WSS data. The polarity of VBIVALID is programmable. This pin is three-stated after a

RESET or software reset and should be pulled high through a 10k resistor.

INTREQ

10k

 Pullup

Interrupt Request Output. This is an open-drain output and requires an external 10k

 pull-

up resistor to VCC.

CLK2

2x pixel clock input. This clock must be a continuous, free-running clock. Refer to Table 1

for allowable CLK2 frequencies for each video standard and aspect ratio. For best

performance, use termination resistor(s) to minimize pulse overshoot and reflections.

RESET

Reset control input. A logical zero for a minimum of four CLK2 cycles resets the device.

RESET must be a logical one for normal operation.

10k

 Pullup

 Pulldown

I2C slave address select input. This was formerly the WPE pin on HMP8112/15 decoders.

If the SA pin is pulled low, the I2C address is 1000100xB or 88H. If the SA pin is pulled high,

the address is 1000101xB or 8AH. (The ‘x’ bit is the address is the I2C read flag.)

SDA

I/O

 Pullup

I2C data input/output. This pin should be pulled high through a 4k

 resistor.

SCL

 Pullup

I2C clock input. This pin should be pulled high through a 4k

 resistor.

VAA

2, 12, 14

0.1µF

to AGND

Analog power supply pins. All VAA pins must be connected together.

AGND

1, 3, 10, 11,

15,16, 21, 22,

23, 24

none

Analog ground pins. All AGND pins must be connected together. Refer to Applications

section for recommended grounding scheme.

VCC

26, 31,37, 52,

59, 68, 75, 79

Digital power supply pins. All VCC pins must be connected together.

GND

25, 33, 35, 36,

39, 46, 53, 62,

69, 72, 80

Digital ground pins. All GND pins must be connected together.

4, 13, 18,

20, 30, 32,

73, 74, 77

No Connect pins. These pins may be left floating or tied to GND.

Pin Descriptions (Continued)

NAME

NUMBER

I/O

PASSIVE

DESCRIPTION

HMP8117 Datasheet(PDF) 39 Page - Renesas Technology Corp

HMP8117 Datasheet(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

Datasheet Download

Link URL