HMP8117

FN4643 Rev 4.00

Page 13 of 45

July 29, 2009

NOTES:

9. Y0 is the first active luminance pixel data of a line. Cb0 and Cr0 are first active chrominance pixel data in a line. Cb and Cr will alternate every

cycle due to the 4:2:2 subsampling.

10. BLANK is asserted per Figure 7.

FIGURE 10. OUTPUT TIMING FOR 16-BIT YCbCr MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

Y0

Cb0

CLK

DVALID

BLANK

P15-P8

P7-P0

tDVLD

Y1

Y2

Y3

Y4

Cr0

Cb2

Cr2

Cb4

NOTE:

11. BLANK is asserted per Figure 7.

FIGURE 11. OUTPUT TIMING FOR 16-BIT [15-BIT] RGB MODE (DVLD_LTC = 0, DVLD_DCYC = 0)

R0

G0

CLK

DVALID

P15-P11

P10-P5

tDVLD

R1

R2

R3

R4

G1

G2

G3

G4

B0

P4-P0

B1

B2

B3

B4

[P9-P5]

[P14-P10]