IMX8XLB0IEC datasheet(21/112 Pages) NXP

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• Prevention of the device from booting

• Irreversible damage to the processor

3.2.1 Power-up sequence

The device has the following power-up sequence requirements:

• Supply group 0 (SNVS) must be powered first. The supply on the 1p8v cap after

the LDO needs to be above minimum supply before this can be considered active.

It is expected that group 0 will typically remain always on after the first power-

on. If its wished to power off this supply then it needs to be entirely powered off

before a reset. Refer to the Power-down sequence .

• Supply group 1 (MAIN, VDD_ANA0_1P8 and VDD_ANA1_1P8) and group 0

must both be powered to their nominal values prior to boot. They must power up

after or simultaneously with group 0.

• Supply group 2 (MEMC, I/O’s and DDR interface) consists of those modules

required to start the boot process by accessing external storage devices. These

must be fully powered prior to POR release if booting from any device. For

8XLite, the DB is in VDD_MEMC so nothing can boot without it. They must

power up after or simultaneously with group 1.

• Supply group 3 consists of the remaining portions of the SoC. This includes

nonboot I/O voltages and supplies for the major computational units. These can

be sequenced in any order and as required to perform the desired functions for the

intended application. They must power up after or simultaneously with group 2.

Note

The definition of "power-up" refers to a stable voltage

operating within the range defined in Table 5. This should

be taken into consideration, along with the different

capacitive loading on each rail, if considering simultaneous

switch-on of the different supply groups.

3.2.2 Power-down sequence

The device processor has the following power-down sequence requirements:

Electrical characteristics

i.MX 8XLite Industrial Applications Processors, Rev. 2, 03/2023

NXP Semiconductors

IMX8XLB0IEC Datasheet(PDF) 21 Page - NXP Semiconductors