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IMX8XLB0IEC Datasheet(PDF) 40 Page - NXP Semiconductors |
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IMX8XLB0IEC Datasheet(HTML) 40 Page - NXP Semiconductors |
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40 / 112 page ![]() 1. As programmed in the associated IOMUX (PDRV field) register. 3.7.1.2 Single-voltage 1.8 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 1.8 V). Table 31. Single-voltage GPIO 1.8 V output impedance DC parameters Parameter Symbol Test conditions Typical Units Output impedance ZO 1 DSE=000 200 Ω 1 DSE=001 100 1 DSE=010 55 1 DSE=011 40 1 DSE=100 30 1 DSE=101 24 1 DSE=110 20 1 DSE=111 18 1. As programmed in the associated IOMUX (DSE field) register. 3.7.1.3 Single-voltage 3.3 V GPIO output buffer drive strength The following table shows the GPIO output buffer drive strength (OVDD 3.3 V). Table 32. Single-voltage GPIO 3.3 V output impedance DC parameters Parameter Symbol Test conditions Typical Units Output impedance ZO 1 DSE=00 400 Ω 1 DSE=01 200 1 DSE=10 100 1 DSE=11 50 1. As programmed in the associated IOMUX (DSE field) register. 3.7.2 DDR I/O output buffer impedance The following tables show DDR3L and LPDDR4 I/O output buffer impedance of the device. The ZQ Calibration cell uses a single register (ZQnPR0) to determine the target output buffer impedances of the pull-up driver and the pull-down driver, as well as the target on-die termination impedance. The resulting calibration setting is then applied to all DDR pads within the PHY complex. Electrical characteristics 40 i.MX 8XLite Industrial Applications Processors, Rev. 2, 03/2023 NXP Semiconductors |
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