X40410 datasheet(11/24 Pages) RENESAS

11 / 24 page

X40410, X40411, X40414, X40415

FN8116 Rev 0.00

Page 11 of 24

March 28, 2005

Stops and Write Modes

Stop conditions that terminate write operations must be

sent by the master after sending at least 1 full data byte

plus the subsequent ACK signal. If a stop is issued in the

middle of a data byte, or before 1 full data byte plus its

associated ACK is sent, then the device will reset itself

without performing the write. The contents of the array

will not be effected.

Acknowledge Polling

The disabling of the inputs during high voltage cycles

can be used to take advantage of the typical 5ms write

cycle time. Once the stop condition is issued to indicate

the end of the master’s byte load operation, the device

initiates the internal high voltage cycle. Acknowledge

polling can be initiated immediately. To do this, the mas-

ter issues a start condition followed by the Slave

Address Byte for a write or read operation. If the device

is still busy with the high voltage cycle then no ACK will

be returned. If the device has completed the write opera-

tion, an ACK will be returned and the host can then pro-

ceed with the read or write operation. See Figure 12.

Serial Read Operations

Read operations are initiated in the same manner as

write operations with the exception that the R/W bit of

the Slave Address Byte is set to one. There are three

basic read operations: Current Address Reads, Random

Reads, and Sequential Reads.

Current Address Read

Internally the device contains an address counter that

maintains the address of the last word read incremented

by one. Therefore, if the last read was to address n, the

next read operation would access data from address

n+1. On power-up, the address of the address counter is

undefined, requiring a read or write operation for initial-

ization.

Upon receipt of the Slave Address Byte with the R/W bit

set to one, the device issues an acknowledge and then

transmits the eight bits of the Data Byte. The master ter-

minates the read operation when it does not respond

with an acknowledge during the ninth clock and then

issues a stop condition. See Figure 13 for the address,

acknowledge, and data transfer sequence.

Figure 12. Acknowledge Polling Sequence

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read oper-

ation, the master must either issue a stop condition

during the ninth cycle or hold SDA HIGH during the ninth

clock cycle and then issue a stop condition.

Random Read

Random read operation allows the master to access any

memory location in the array. Prior to issuing the Slave

Address Byte with the R/W bit set to one, the master must

first perform a “dummy” write operation. The master issues

the start condition and the Slave Address Byte, receives an

acknowledge, then issues the Word Address Bytes. After

acknowledging receipts of the Word Address Bytes, the

master immediately issues another start condition and the

Slave Address Byte with the R/W bit set to one. This is fol-

lowed by an acknowledge from the device and then by the

eight bit word. The master terminates the read operation by

not responding with an acknowledge and then issuing a

stop condition. See Figure 14 for the address, acknowl-

edge, and data transfer sequence.

ACK

Returned?

Issue Slave Address

Byte (Read or Write)

Byte Load Completed

by Issuing STOP.

Enter ACK Polling

Issue STOP

Issue START

YES

High Voltage Cycle

Complete. Continue

Command Sequence?

Issue STOP

Continue Normal

Read or Write

Command Sequence

PROCEED

YES

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