ADM1062ASU datasheet(21/32 Pages) AD

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Preliminary Technical Data

ADM1062

Rev. PrJ | Page 21 of 32

Figure 31. Monitoring Fault Detector

TIMEOUT DETECTOR

This block is included to allow the user to trap a failure to make

proper progress through an up or down sequence.

In the example application we can see the timeout next state

transition being used from the EN3V3 and EN2V5 states. In the

case of the EN3V3 state, the signal 3V3ON is asserted on entry

to this state (on the PDO1 output pin) to turn on a 3.3V supply.

This supply rail is connected to the VP2 pin and the End of Step

detector is looking for the VP2 to go “good” (going above its’ UV

threshold, which will be set on the Supply Fault Detector (SFD)

attached to that pin). Progress forward in the up sequence is

made when this change is detected.

If, however, the supply failed to go “good” – perhaps because of a

short circuit over-loading this supply – then the timeout block

allows this problem to be trapped. In the example shown, if the

3.3V supply does not go good within 10ms then the SE moves

to the DIS3V3 state and turns off this supply by bringing PDO1

low. It also indicates that a fault has occurred by taking PDO3

high. Timeout delays of between 0µs and 400ms can be

programmed.

CLOSED LOOP SUPPLY MARGINING

It is often necessary for the system designer to be able to adjust

supplies, either to optimize their level, or to force them away

from nominal values to characterize the system performance

under these conditions. This is a function typically performed at

In- Circuit Test (ICT), for instance, where the manufacturer

wishes to guarantee that the product under test functions

correctly at, say, nominal supplies −10%. The ADM1062

incorporates all the circuits required to do this, with a 12-bit

successive approximation ADC to read back the level of any of

the supervised voltages, and six voltage output DACs (DAC1–

DAC6) which can be used to adjust supply levels. These circuits

can be used along with some other “intelligence” such as a

microcontroller to implement a closed loop margining system

which will allow any dc-dc supply to be set to any voltage,

accurate to within ±0.5% of the target.

Figure 32. Closed Loop Margining System using ADM1062

The simplest circuit to implement this function is an

attenuation resistor to connect the DACn pin to the feedback

node of a dc-dc converter. When the DACn output voltage is set

equal to the feedback voltage, no current is fed in to this node

and the dc-dc output voltage will not change. Taking DACn

above the feedback voltage forces current into the feedback

node and the output of the dc-dc converter will be forced to fall

to compensate for this. The dc-dc output can be forced high by

setting the DACn output voltage lower than the feedback node

voltage. The series resistor can be split in two and node between

them decoupled with a capacitor to ground. This will help to

decouple any noise picked up from the board. PSRR from

ADM1062 supply to the dac output is greater than 80dB at dc

but decoupling to a ground local to the dc-dc converter is also

recommended.

Then the simplest algorithm to implement closed loop

margining is as follows:

Disable the six DACn outputs.

Set DAC output voltage equal to the voltage on the

feedback node.

Enable the DAC.

Read the voltage at the dc-dc output (which will be

connected to one of the VP1–4,VH or VX1–5 pins).

If necessary, modify the DACn output code up or down to

adjust the dc-dc output voltage, otherwise, stop since target

voltage has been reached.

Set the DAC output voltage to a value which alters the

supply output by the required amount (eg) ±5%.

Repeat from 4.

Steps 1-3 ensure that when the DACn output buffer is turned on

it has very little effect on the dc-dc output. The dac output

buffer has been designed to power up without glitching. It does

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