ISL71040M

1. Overview

R34DS0001EU0101 Rev.1.01

Page 4 of 23

Dec 15, 2022

1.3

Pin Descriptions

Pin Number

Pin Name

ESD Circuit

Description

1

VDD

3

Supply for the ISL71040M internal linear regulator. Locally bypass the supply to VDD using

at least a 4.7µF ceramic capacitor.

2

IN

3

Non-inverting input pin that controls the OUTH and OUTL outputs. This input has

TTL/CMOS type thresholds. When using the ISL71040M in an inverting application, tie this

pin to VDD to enable the outputs.

3

INB

3

Inverting input pin that controls the OUTH and OUTL outputs. This input has TTL/CMOS

type thresholds. When using the ISL71040M in a non-inverting application, tie this pin to

VSS to enable the outputs.

4

VSS

4

Supply ground. Connect this pin to VSSP from the PCB ground plane.

5

VSSP

4

Power supply ground. Connect this pin to VSS from the PCB ground plane.

6

OUTL

2

Output low pin that is the gate driver turn-off output. Connect this pin to the gate of the GaN

FET with a short, low inductance path. A series gate resistor can be used to adjust the

turn-off speed.

7

OUTH

1

Output high pin that is the gate driver turn-on output. Connect this pin to the gate of the GaN

FET with a short, low inductance path. A series gate resistor can be used to adjust the

turn-on speed.

8

VDRV

1

Internal linear regulator output and the gate drive voltage. Locally bypass this pin using at

least a 4.7µF ceramic capacitor; 2µF to 10µF with variability.

-

EPAD

4

The exposed pad should be connected externally to VSSP. Put as many vias as possible in

this pad connecting to other PCB layers to improve heat dissipation.

ESD Circuits:

Circuit 1

Circuit 3

Circuit 4

Circuit 2

VSS

VSSP

VSSP

VSS

PIN #

PIN #

PIN #

7V

7V

7V

7V

7V

VSS

VSSP

VSS

VSSP

17V

17V

VDRV