LP3972 datasheet(44/59 Pages) NSC

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2C Compatible Interface (Continued)

INTERRUPT STATUS REGISTER ISRA

This register specifies the status bits for the interrupts generated by the PMIC. Thermal warning of the IC, GPIO1, GPIO2,

PWR_ON pin, TEST_JIG factory programmable on signal, and the SPARE pin.

Interrupt Status Register ISRA 8h’88

Bit

Designation

Reserved

T125

GPI2

GPI1

WU3L

WUPS

WUPT

WUPS

Reset Value

Interrupt Status Register ISRA 8h’88 Definitions

Bit

Access

Name

Description

—

Reserved

T125

Status bit for thermal warning PMIC T>125C

0 = PMIC Temp. < 125˚C

1 = PMIC Temp. > 125˚C

GPI2

Status bit for the input read in from GPIO 2 when set as Input

0 = GPI2 Logic Low

1 = GPI2 Logic High

GPI1

Status bit for the input read in from GPIO 1 when set as Input

0 = GPI1 Logic Low

1 = GPI1 Logic High

WU3L

PWR_ON Pin long pulse Wake Up Status

0 = No wake up event

1 = Long pulse wake up event

WUPS

PWR_ON Pin Short pulse Wake Up Status

0 = No wake up event

1 = Short pulse wake up event

WUPT

TEST_JIG Pin Wake Up Status

0 = No wake up event

1 = Wake up event

WUPS

SPARE Pin Wake Up Status

0 = No wake up event

1 = Wake up event

LP3972 Datasheet(PDF) 44 Page - National Semiconductor (TI)

LP3972 Datasheet(HTML) 44 Page - National Semiconductor (TI)

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