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LP3972 Datasheet(PDF) 48 Page - National Semiconductor (TI) |
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LP3972 Datasheet(HTML) 48 Page - National Semiconductor (TI) |
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48 / 59 page  LP3972 Controls DIGITAL INTERFACE CONTROL SIGNALS Signal Definition Active State Signal Direction SYS_EN High Voltage Power Enable High Input PWR_EN Low Voltage Power Enable High Input SCL Serial Bus Clock Line Clock Input SDA Serial Bus Data Line Bidirectional nRSTI Forces an unconditional hardware reset Low Input nRSTO Forces an unconditional hardware reset Low Output nBATT_FLT Main Battery removed or discharged indicator Low Output PWR_ON Wakeup Input to CPU High Input nTEST_JIG Wakeup Input to CPU Low Input SPARE Wakeup Input to CPU High Input EXT_WAKEUP Wake-Up Output for application processor High Output GPIO1 / nCHG_EN General Purpose I/O /External Back-up Battery Charger enable — Bidirectional /Input GPIO2 General Purpose I/O — Bidirectional POWER DOMAIN ENABLES PMU Output HW Enable SW Enable LDO_RTC — — LDO1(V CC_MVT) SYS_EN LDO1_EN LDO2 SYS_EN LDO2_EN LDO3 SYS_EN LDO3_EN LDO4 SYS_EN LDO4_EN LDO5 (V CC_SRAM) PWR_EN S_EN Buck1 (V CC_APPS) PWR_EN A_EN BUCK2 SYS_EN B2_EN BUCK3 SYS_EN B3_EN POWER DOMAINS SEQUENCING (DELAY) By default SYS_EN must be on to have PWR_EN enable but this feature can be switched off by register bit BP_SYS. By default SYS_EN enables LDO1 always first and after a typical of 1 ms delay others. Also when SYS_EN is set off the LDO1 will go off last. This function can be switched off or delay can be changed by DELAY bits via serial interface as seen on table below. 8h’80 Bit 5:4 DELAY bits ‘00’ ‘01’ ‘10’ ‘11’ Delay, ms 0 0.5 1.0 1.5 LDO_RTC TRACKING (nIO_TRACK) LP3972 has a tracking function (nIO_TRACK). When en- abled, LDO_RTC voltage will track LDO3 voltage within 200 mV down to 2.8V when LDO3 is enabled. This function can be switched on/off by nIO_TRACK register bit BPTR. POWER SUPPLY ENABLE SYS_EN and PWR_EN can be changed by programmable register bits. www.national.com 48 |
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