Nexperia

74ALVC74

Dual D-type flip-flop with set and reset; positive-edge trigger

5.2. Pin description

Table 2. Pin description

Symbol

Pin

Description

1RD

1

asynchronous reset-direct input (active-LOW)

1D

2

data input

1CP

3

clock input (LOW-to-HIGH), edge-triggered

1SD

4

asynchronous set-direct input (active-LOW)

1Q

5

true flip-flop output

1Q

6

complement flip-flop output

GND

7

ground (0 V)

2Q

8

complement flip-flop output

2Q

9

true flip-flop output

2SD

10

asynchronous set-direct input (active-LOW)

2CP

11

clock input (LOW-to-HIGH), edge-triggered

2D

12

data input

2RD

13

asynchronous reset-direct input (active-LOW)

VCC

14

supply voltage

6. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition;

nQn+1 = state after the next LOW-to-HIGH CP transition

Input

Output

nSD

nRD

nCP

nD

nQ

nQ

nQn+1

nQ n+1

L

H

X

X

H

L

-

-

H

L

X

X

L

H

-

-

L

L

X

X

H

H

-

-

H

H

↑

L

-

-

L

H

H

H

↑

H

-

-

H

L

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter

Conditions

Min

Max

Unit

VCC

supply voltage

-0.5

+4.6

V

VI

input voltage

[1]

-0.5

+4.6

V

[1]

-0.5

VCC + 0.5 V

VO

output voltage

Power-down mode; VCC = 0 V

[1]

-0.5

+4.6

V

IIK

input clamping current

VI < 0 V

-50

-

mA

IOK

output clamping current

VO > VCC or VO < 0 V

-

±50

mA

IO

output current

VO = 0 V to VCC

-

±50

mA

ICC

supply current

-

100

mA

74ALVC74

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 6 — 27 July 2021

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