Nexperia

74ALVC74

Dual D-type flip-flop with set and reset; positive-edge trigger

10.1. Waveforms and test circuit

aaa-008840

GND

VI

GND

VI

VOH

VOH

VOL

VOL

nCP input

nQ output

nQ output

nD input

tsu

tPLH

tPHL

VM

VM

tW

tPHL

VM

VM

th

tsu

1/fmax

tPLH

th

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 8. Clock pulse (nCP) to output (nQ, nQ) propagation delays, nCP pulse width, the nD to nCP set-up times,

the nCP to nD hold times and maximum frequency

trec

VM

VM

VM

aaa-008842

tPHL

tPLH

tPHL

tPLH

tW

tW

VM

VI

VI

VI

VOH

VOL

VOL

VOH

VM

GND

GND

GND

nCP input

nSD input

nRD input

nQ output

nQ output

Measurement points are given in Table 8.

Fig. 9. Set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, set (nSD) and reset (nRD) pulse

widths and nRD to nCP recovery time

74ALVC74

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Product data sheet

Rev. 6 — 27 July 2021

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