ADT7467 datasheet(13/80 Pages) AD

13 / 80 page

ADT7467

Rev. 0| Page 13 of 80

The slave asserts ACK on SDA.

The master sends a data byte.

The slave asserts ACK on SDA.

The master asserts a stop condition on SDA to end the

transaction.

This operation is illustrated in Figure 20.

SLAVE

ADDRESS

SLAVE

ADDRESS

DATA

SA P

Figure 20. Single Byte Write to a Register

READ OPERATIONS

The ADT7467 uses the following SMBus read protocols.

Receive Byte

This operation is useful when repeatedly reading a single

In this operation, the master device receives a single byte from a

slave device, as follows:

The master device asserts a start condition on SDA.

The master sends the 7-bit slave address followed by the

read bit (high).

The addressed slave device asserts ACK on SDA.

The master receives a data byte.

The master asserts NO ACK on SDA.

The master asserts a stop condition on SDA and the

transaction ends.

In the ADT7467, the receive byte protocol is used to read a

single byte of data from a register whose address has previously

been set by a send byte or write byte operation. This operation

is illustrated in Figure 21.

SLAVE

ADDRESS

SR A

DATA

Figure 21. Single Byte Read from a Register

Alert Response Address

Alert response address (ARA) is a feature of SMBus devices that

allows an interrupting device to identify itself to the host when

multiple devices exist on the same bus.

The SMBALERT output can be used as either an interrupt

output or an SMBALERT. One or more outputs can be

connected to a common SMBALERT line connected to the

master. If a device’s SMBALERT line goes low, the following

procedure occurs:

SMBALERT is pulled low.

The master initiates a read operation and sends the alert

response address (ARA = 0001 100). This is a general call

address that must not be used as a specific device address.

The device whose SMBALERT output is low responds to

the alert response address, and the master reads its device

address. The address of the device is now known and can

be interrogated in the usual way.

If more than one device’s SMBALERT output is low, the

one with the lowest device address has priority in accor-

dance with normal SMBus arbitration.

Once the ADT7467 has responded to the alert response

address, the master must read the status registers and the

SMBALERT is cleared only if the error condition has gone

away.

SMBUS TIMEOUT

The ADT7467 includes an SMBus timeout feature. If there is no

SMBus activity for 35 ms, the ADT7467 assumes that the bus is

locked and releases the bus. This prevents the device from

locking or holding the SMBus expecting data. Some SMBus

controllers cannot handle the SMBus timeout feature, so it can

be disabled.

Configuration Register 1(Reg. 0x40)

<6> TODIS = 0,

SMBus timeout enabled (default).

<6> TODIS = 1,

SMBus timeout disabled.

VOLTAGE MEASUREMENT INPUT

The ADT7467 has one external voltage measurement channel. It

can also measure its own supply voltage, VCC. Pin 14 can meas-

ure VCCP. The VCC supply voltage measurement is carried out

through the VCC pin (Pin 3). Setting Bit 7 of Configuration

ADT7467 and be measured without overranging the VCC

measurement channel. The VCCP input can be used to monitor a

chipset supply voltage in computer systems.

ANALOG-TO-DIGITAL CONVERTER

All analog inputs are multiplexed into the on-chip, successive

approximation, analog-to-digital converter. This has a resolu-

tion of 10 bits. The basic input range is 0 V to 2.25 V, but the

input has built-in attenuators to allow measurement of VCCP

without any external components. To allow for the tolerance of

the supply voltage, the ADC produces an output of 3/4 full scale

(decimal 768 or 300 hex) for the nominal input voltage and so

has adequate headroom to deal with overvoltages.

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