STM32H7 datasheet(138/357 Pages) STMICROELECTRONICS

138 / 357 page

Electrical characteristics (rev Y)

STM32H742xI/G STM32H743xI/G

138/357

DS12110 Rev 10

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters. The

coverage of these requirements for FT I/Os is shown in Figure 22.

VHYS(2)

TT_xx, FT_xxx and NRST I/O

input hysteresis

1.62 V< VDDIOx <3.6 V

250

BOOT0 I/O input hysteresis

200

Ilkg(4)

FT_xx Input leakage current(2)

0< VIN ≤ Max(VDDXXX)(9)

+/-250

Max(VDDXXX) < VIN ≤ 5.5 V

(5)(6)(9)

1500

FT_u IO

0< VIN ≤ Max(VDDXXX)(9)

+/- 350

Max(VDDXXX) < VIN ≤ 5.5 V

(5)(6)(9)

5000(7)

TT_xx Input leakage current

0< VIN ≤ Max(VDDXXX) (9)

+/-250

VPP (BOOT0 alternate function)

0< VIN ≤ VDDIOX

VDDIOX < VIN ≤ 9 V

RPU

Weak pull-up equivalent

resistor(8)

VIN=VSS

kΩ

RPD

Weak pull-down equivalent

resistor(8)

VIN=VDD(9)

CIO

I/O pin capacitance

1. Compliant with CMOS requirement.

2. Guaranteed by design.

3. VDDIOx represents VDDIO1, VDDIO2 or VDDIO3. VDDIOx= VDD.

4. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following

formula: ITotal_Ikg_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).

5. All FT_xx IO except FT_lu, FT_u and PC3.

6. VIN must be less than Max(VDDXXX) + 3.6 V.

7. To sustain a voltage higher than MIN(VDD, VDDA, VDD33USB) +0.3 V, the internal pull-up and pull-down resistors must be

disabled.

8. The pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This

PMOS/NMOS contribution to the series resistance is minimal (~10% order).

9. Max(VDDXXX) is the maximum value of all the I/O supplies.

Table 60. I/O static characteristics (continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

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