August 28, 2006 S25FL016A_00_C0

S25FL016A

11

Da ta

Shee t

(Prelim i nar y )

– Write Disable (WRDI)

– Write Status Register (WRSR)

Software Protected Mode (SPM): The Block Protect (BP2, BP1, BP0) bits define the section of the

memory array that can be read but not programmed or erased. Table 7.1 shows the sizes and address

ranges of protected areas that are defined by Status Register bits BP2:BP0.

Hardware Protected Mode (HPM): The Write Protect (W#) input and the Status Register Write Disable

(SRWD) bit together provide write protection.

Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands

consist of a clock pulse count that is a multiple of eight before executing them.

7.7

Hold Mode (HOLD#)

The Hold input (HOLD#) stops any serial communication with the device, but does not terminate any Write

Status Register, program or erase operation that is currently in progress.

The Hold mode starts on the falling edge of HOLD# if SCK is also low (see Figure 7.1, on page 11, standard

use). If the falling edge of HOLD# does not occur while SCK is low, the Hold mode begins after the next falling

edge of SCK (non-standard use).

The Hold mode ends on the rising edge of HOLD# signal (standard use) if SCK is also low. If the rising edge

of HOLD# does not occur while SCK is low, the Hold mode ends on the next falling edge of CLK (non-

standard use) See Figure 7.1.

The SO output is high impedance, and the SI and SCK inputs are ignored (don’t care) for the duration of the

Hold mode.

CS# must remain low for the entire duration of the Hold mode to ensure that the device internal logic remains

unchanged. If CS# goes high while the device is in the Hold mode, the internal logic is reset. To prevent the

device from reverting to the Hold mode when device communication is resumed, HOLD# must be held high,

followed by driving CS# low.

Figure 7.1 Hold Mode Operation

Table 7.1 S25FL016A Protected Area Sizes

Status Register

Block Protect Bits

Memory Array

Protected

Portion of

Total Memory

Area

BP2

BP1

BP0

Protected

Address Range

Protected

Sectors

Unprotected

Address Range

Unprotected

Sectors

0

0

0

None

(0)

000000h–1FFFFFh

SA31:SA0

0

0

0

1

1F0000h–1FFFFFh

(1) SA31

000000h–1EFFFFh

SA30:SA0

1/32

0

1

0

1E0000h–1FFFFFh

(2) SA31:SA30

000000h–1DFFFFh

SA29:SA0

1/16

0

1

1

1C0000h–1FFFFFh

(4) SA31:SA28

000000h–1BFFFFh

SA27:SA0

1/8

1

0

0

180000h–1FFFFFh

(8) SA31:SA24

000000h–17FFFFh

SA23:SA0

1/4

1

0

1

100000h–1FFFFFh

(16) SA31:SA16

000000h–0FFFFFh

SA15:SA0

1/2

1

1

0

000000h–1FFFFFh

(32) SA31:SA0

None

None

All

1

1

1

000000h–1FFFFFh

(32) SA31:SA0

None

None

All

SCK

HOLD#

Hold

Condition

(standard use)

Hold

Condition

(non-standard use)